 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| M24LR64-R 64 Kbit EEPROM with password protection & dual interface: 400 kHz IC serial bus & ISO 15693 RF protocol at 13.56 MHz Features I2C interface Two-wire I2C serial interface supports 400 kHz protocol Single supply voltage: - 1.8 V to 5.5 V Byte and Page Write (up to 4 bytes) Random and Sequential Read modes Self-timed programming cycle Automatic address incrementing Enhanced ESD/latch-up protection UFDFPN8 (MB) 2 x 3 mm SO8 (MN) 150 mils width Contactless interface ISO 15693 and ISO 18000-3 mode 1 compliant 13.56 MHz 7k Hz carrier frequency To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands Internal tuning capacitance: 27.5 pF 64-bit unique identifier (UID) Read Block & Write (32-bit Blocks) TSSOP8 (DW) Memory 64 Kbit EEPROM organized into: - 8192 bytes in I2C mode - 2048 blocks of 32 bits in RF mode Write time - I2C: 5 ms (Max.) - RF: 5.75 ms including the internal Verify time More than 1 Million write cycles Sawn wafer on UV tape Multiple password protection in RF mode Single password protection in I2C mode More than 40-year data retention Package - ECOPACK2(R) (RoHS compliant and Halogen-free) June 2010 Doc ID 15170 Rev 10 1/128 www.st.com 1 Contents M24LR64-R Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 2.2 2.3 2.4 2.5 2.6 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chip Enable (E0, E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 2.6.2 2.6.3 2.6.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 4 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 4.2 4.3 4.4 4.5 M24LR64-R RF block security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Example of the M24LR64-R security protection . . . . . . . . . . . . . . . . . . . . 25 I2C_Write_Lock bit area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 M24LR64-R I2C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.5.1 4.5.2 I2C Present Password command description . . . . . . . . . . . . . . . . . . . . 27 I2C Write Password command description . . . . . . . . . . . . . . . . . . . . . . 28 5 I2C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 15170 Rev 10 2/128 M24LR64-R Contents 5.8 5.9 5.10 5.11 5.12 5.13 5.14 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 34 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 7 User memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 7.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2.1 7.2.2 7.2.3 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 9 Communication signal from VCD to M24LR64-R . . . . . . . . . . . . . . . . . 40 Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 9.2 9.3 9.4 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VCD to M24LR64-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Communications signal from M24LR64-R to VCD . . . . . . . . . . . . . . . . 47 10.1 10.2 10.3 Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1.1 11.1.2 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 11.3 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Doc ID 15170 Rev 10 3/128 Contents M24LR64-R 11.4 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 M24LR64-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.10 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.11 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.12 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13 14 15 Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.1 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 16 17 M24LR64-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 M24LR64-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 17.1 17.2 17.3 17.4 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.1 18.2 18.3 Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 62 Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4/128 Doc ID 15170 Rev 10 M24LR64-R Contents 19 Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 19.1 Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 20 Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 20.1 20.2 Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 21 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 21.1 Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 22 23 24 25 Request processing by the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 69 Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25.1 25.2 25.3 t1: M24LR64-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 t3: VCD new request delay in the absence of a response from the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 26 Commands codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Doc ID 15170 Rev 10 5/128 Contents M24LR64-R 26.14 Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 26.15 Lock-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 26.16 Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 26.17 Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 26.18 Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 26.19 Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 26.20 Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 27 28 29 30 31 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 RF DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 123 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Appendix B CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 B.1 B.2 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 126 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6/128 Doc ID 15170 Rev 10 M24LR64-R List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Sector Security Status Byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Read / Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Password Control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 M24LR64-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M24LR64-R sector security protection after a valid presentation of password 1 . . . . . . . . 25 I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 M24LR64-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 M24LR64-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 67 Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Stay Quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 77 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 77 Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 79 Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 79 Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 81 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 82 Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Doc ID 15170 Rev 10 7/128 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. M24LR64-R Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 83 Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 84 Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Lock AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 89 Write DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 91 Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Get System Info response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . 93 Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . . 95 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . . 96 Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . . 97 Write-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . 97 Lock-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Lock-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . 99 Lock-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . 99 Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 101 Present-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . 101 Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 103 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . 103 Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Fast Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 107 Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 108 Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Initiate Initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I2C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8/128 Doc ID 15170 Rev 10 M24LR64-R Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. List of tables AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 I2C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 I2C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RF AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 RF DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SO8N - 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 118 UFDFPN8 (MLP8) - Ultra thin fine pitch dual flat package no lead 2 x 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 120 Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Ordering information scheme for bare die devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Doc ID 15170 Rev 10 9/128 List of figures M24LR64-R List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 I2C Present Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 I2C Write Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 31 Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 33 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Logic 0, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Logic 1, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Logic 0, low data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Logic 1, low data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Start of frame, high data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Start of frame, low data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 End of frame, high data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 End of frame, high data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 End of frame, low data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 End of frame, low data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 M24LR64-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10/128 Doc ID 15170 Rev 10 M24LR64-R Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. List of figures M24LR64-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 M24LR64-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 68 Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Stay Quiet frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . 76 Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 78 Write Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 80 Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . 82 Select frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Reset to Ready frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . 84 Write AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 86 Lock AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 88 Write DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 90 Lock DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . 92 Get System Info frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . . . . 94 Get Multiple Block Security Status frame exchange between VCD and M24LR64-R . . . . 96 Write-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 98 Lock-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 100 Present-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . 102 Fast Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . 104 Fast Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 106 Fast Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . 108 Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . 110 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 M24LR64-R synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 118 UFDFPN8 (MLP8) - Ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 120 Doc ID 15170 Rev 10 11/128 Description M24LR64-R 1 Description The M24LR64-R device is a dual-interface, electrically erasable programmable memory (EEPROM). It features an I2C interface and can be operated from a VCC power supply. It is also a contactless memory powered by the received carrier electromagnetic wave. The M24LR64-R is organized as 8192 x 8 bits in the I2C mode and as 2048 x 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode. Figure 1. Logic diagram VCC 2 E0-E1 SCL M24LR64-R SDA AC0 AC1 VSS AI15106b I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64-R is accessed via the 13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modulation (ASK: amplitude shift keying). The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding mode. Outgoing data are generated by the M24LR64-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR64-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR64-R supports the 53 Kbit/s in high data rate mode in one subcarrier frequency at 423 kHz. The M24LR64-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface. 12/128 Doc ID 15170 Rev 10 M24LR64-R Table 1. Signal names Signal name E0, E1 SDA SCL AC0, AC1 VCC VSS Function Chip Enable Serial Data Serial Clock Antenna coils Supply voltage Ground Input I/O Input I/O Description Direction Figure 2. 8-pin package connections E0 AC0 AC1 VSS 1 2 3 4 8 7 6 5 VCC E1 SCL SDA AI15107 1. See Package mechanical data section for package dimensions, and how to identify pin-1. Doc ID 15170 Rev 10 13/128 Signal description M24LR64-R 2 2.1 Signal description Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial Data (SDA) This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). 2.3 Chip Enable (E0, E1) These input signals are used to set the value that is to be looked for on the two least significant bits (b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code as shown in Figure 3. When not connected (left floating), these inputs are read as low (0,0). Figure 3. Device select code VCC VCC M24xxx Ei M24xxx Ei VSS VSS Ai12806 2.4 Antenna coil (AC0, AC1) These inputs are used to connect the device to an external coil. When correctly tuned, the coil is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1 protocols. 2.5 VSS ground VSS is the reference for the VCC supply voltage. 14/128 Doc ID 15170 Rev 10 M24LR64-R Signal description 2.6 Note: Supply voltage (VCC) This pin can be connected to an external DC supply voltage. An internal voltage regulator allows the external voltage applied on VCC to supply the M24LR64-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the VCC pin. 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 100). To maintain a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal IC write cycle (tW). 2.6.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/s. 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power-on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 100). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode, however, the device must not be accessed until VCC has reached a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decay of VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). Doc ID 15170 Rev 10 15/128 Signal description Figure 4. Bus line pull-up resistor (k ) 100 When tLOW = 1.3 s (min value for fC = 400 kHz), the Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left. M24LR64-R I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) VCC 10 4 k R bu sx C bu s= Here Rbus x Cbus = 120 ns 4 Rbus 00 ns IC bus master SCL SDA M24xxx 1 10 30 pF 100 Bus line capacitor (pF) 1000 Cbus ai14796b Figure 5. I2C bus protocol SCL SDA SDA Input SDA Change Start Condition Stop Condition SCL 1 2 3 7 8 9 SDA MSB ACK Start Condition SCL 1 2 3 7 8 9 SDA MSB ACK Stop Condition AI00792B 16/128 Doc ID 15170 Rev 10 M24LR64-R Table 2. Device select code Device type identifier(1) b7 Device select code 1 b6 0 b5 1 b4 0 Signal description Chip Enable address(2) b3 E2(3) b2 E1 b1 E0 RW b0 RW 1. The most significant bit, b7, is sent first. 2. E0 and E1 are compared against the respective external pins on the memory device. 3. E2 is not connected to any external pin. It is however used to address the M24LR64-R as described in Section 3 and Section 4. Table 3. b15 Address most significant byte b14 b13 b12 b11 b10 b9 b8 Table 4. b7 Address least significant byte b6 b5 b4 b3 b2 b1 b0 Doc ID 15170 Rev 10 17/128 User memory organization M24LR64-R 3 User memory organization The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5. Figure 7 shows the memory sector organization. Each sector can be individually readand/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector. The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user and its value is written by ST on the production line. The M24LR64-R includes an AFI register that stores the application family identifier, and a DSFID register that stores the data storage family identifier used in the anticollision algorithm. The M24LR64-R has four additional 32-bit blocks that store an I2C password plus three RF password codes. Figure 6. Block diagram Row decoder EEPROM AC0 RF AC1 RF VCC Latch Logic I2C SCL SDA VCC VSS ai15123 Power management Contact VCC 18/128 Doc ID 15170 Rev 10 M24LR64-R Figure 7. Memory sector organization Sector 0 1 2 3 60 61 62 63 Area 1 Kbit EEPROM sector 1 Kbit EEPROM sector 1 Kbit EEPROM sector 1 Kbit EEPROM sector 1 Kbit EEPROM sector 1 Kbit EEPROM sector 1 Kbit EEPROM sector 1 Kbit EEPROM sector I2C Password RF Password 1 RF Password 2 RF Password 3 8 bit DSFID 8 bit AFI 64 bit UID User memory organization Sector security status 5 bits 5 bits 5 bits 5 bits 5 bits 5 bits 5 bits 5 bits System System System System System System System ai15124 Sector details The M24LR64-R user memory is divided into 64 sectors. Each sector contains 1024 bits. The protection scheme is described in Section 4: System memory area. In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access are done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to all the 32 blocks contained in the sector. If the sector is not protected, a Write command updates the complete 32 bits of the selected block. In I2C mode, a sector provides 128 bytes that can be individually accessed in read and write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is writeprotected. To access the user memory, the device select code used for any I2C command must have the E2 Chip Enable address at 0. Doc ID 15170 Rev 10 19/128 User memory organization Table 5. Sector number M24LR64-R Sector details RF block address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I2C byte address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 Bits [31:24] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user Bits [23:16] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user Bits [15:8] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user Bits [7:0] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 20/128 Doc ID 15170 Rev 10 M24LR64-R Table 5. Sector number User memory organization Sector details (continued) RF block address 32 33 34 35 1 36 37 38 39 ... ... ... I2C byte address 128 132 136 140 144 148 152 156 ... ... Bits [31:24] user user user user user user user user ... ... Bits [23:16] user user user user user user user user ... ... Bits [15:8] user user user user user user user user ... ... Bits [7:0] user user user user user user user user ... ... Doc ID 15170 Rev 10 21/128 User memory organization Table 5. Sector number M24LR64-R Sector details (continued) RF block address 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 I2C byte address 8064 8068 8072 8076 8080 8084 8088 8092 8096 8100 8104 8108 8112 8116 8120 8124 8128 8132 8136 8140 8144 8148 8152 8156 8160 8164 8168 8172 8176 8180 8184 8188 Bits [31:24] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user Bits [23:16] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user Bits [15:8] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user Bits [7:0] user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user user 63 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 22/128 Doc ID 15170 Rev 10 M24LR64-R System memory area 4 4.1 System memory area M24LR64-R RF block security The M24LR64-R provides a special protection mechanism based on passwords. Each memory sector of the M24LR64-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set. Each memory sector of the M24LR64-R is assigned with a Sector security status byte including a Sector Lock bit, two Password Control bits and two Read/Write protection bits as shown in Table 7. Table 6 describes the organization of the Sector security status byte which can be read using the Read Single Block and Read Multiple Block commands with the Option_flag set to `1'. On delivery, the default value of the SSS bytes is reset to 00h. Table 6. I2C Sector Security Status Byte area byte address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 Bits [31:24] SSS 3 SSS 7 SSS 11 SSS 15 SSS 19 SSS 23 SSS 27 SSS 31 SSS 35 SSS 39 SSS 43 SSS 47 SSS 51 SSS 55 SSS 59 SSS 63 Bits [23:16] SSS 2 SSS 6 SSS 10 SSS 14 SSS 18 SSS 22 SSS 26 SSS 30 SSS 34 SSS 38 SSS 42 SSS 46 SSS 50 SSS 54 SSS 58 SSS 62 Bits [15:8] SSS 1 SSS 5 SSS 9 SSS 13 SSS 17 SSS 21 SSS 25 SSS 29 SSS 33 SSS 37 SSS 41 SSS 45 SSS 49 SSS 53 SSS 57 SSS 61 Bits [7:0] SSS 0 SSS 4 SSS 8 SSS 12 SSS 16 SSS 20 SSS 24 SSS 28 SSS 32 SSS 36 SSS 40 SSS 44 SSS 48 SSS 52 SSS 56 SSS 60 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 Table 7. b7 0 Sector security status byte organization b6 0 b5 0 b4 b3 b2 b1 b0 Sector Lock Read / Write protection bits Password Control bits When the Sector Lock bit is set to `1', for instance by issuing a Lock-sector Password command, the 2 Read/Write protection bits (b1, b2) are used to set the Read/Write access of the sector as described in Table 8. Doc ID 15170 Rev 10 23/128 System memory area Table 8. Sector Lock 0 1 1 1 1 M24LR64-R Read / Write protection bit setting b2, b1 xx 00 01 10 11 Sector access when password presented Read Read Read Read Read Write Write Write Write No Write Sector access when password not presented Read Read Read No Read No Read Write No Write Write No Write No Write The next 2 bits of the Sector security status byte (b3, b4) are the Password Control bits. The value these two bits is used to link a password to the sector as defined in Table 9. Table 9. b4, b3 00 01 10 11 Password Control bits Password The sector is not protected by a Password The sector is protected by the Password 1 The sector is protected by the Password 2 The sector is protected by the Password 3 The M24LR64-R password protection is organized around a dedicated set of commands plus a system area of three password blocks where the password values are stored. This system area is described in Table 10. Table 10. Add 1 2 3 0 Password system area 78 15 16 23 24 31 Password 1 Password 2 Password 3 The dedicated password commands are: Write-sector Password: The Write-sector Password command is used to write a 32-bit block into the password system area. This command must be used to update password values. After the write cycle, the new password value is automatically activated. It is possible to modify a password value after issuing a valid Present-sector Password command. On delivery, the three default password values are set to 0000 0000h and are activated. Lock-sector Password: The Lock-sector Password command is used to set the Sector security status byte of the selected sector. Bits b4 to b1 of the Sector security status byte are affected by the Lock-sector Password command. The Sector Lock bit, b0, is set to `1' automatically. After issuing a Lock-sector Password command, the protection settings of the selected sector are activated. The protection of a locked block cannot be changed in RF mode. A Lock-sector Password command sent to a locked sector returns an error code. 24/128 Doc ID 15170 Rev 10 M24LR64-R System memory area Present-sector Password: The Present-sector Password command is used to present one of the three passwords to the M24LR64-R in order to modify the access rights of all the memory sectors linked to that password (Table 8) including the password itself. If the presented password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector Password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated. Sector security status byte area access conditions in I2C mode: In I2C mode, read access to the Sector security status byte area is always allowed. Write access depends on the correct presentation of the I2C password (see I2C Present Password command description on page 27). To access the Sector security status byte area, the device select code used for any I2C command must have the E2 Chip Enable address at 1. An I2C write access to a Sector security status byte re-initializes the RF access condition to the given memory sector. 4.2 Example of the M24LR64-R security protection Table 11 and Table 12 show the sector security protections before and after a valid Presentsector Password command. Table 11 shows the sector access rights of an M24LR64-R after power-up. After a valid Present-sector Password command with password 1, the memory sector access is changed as shown in Table 12. Table 11. Sector address 0 1 2 3 4 Protection: Standard Protection: Pswd 1 Protection: Pswd 1 Protection: Pswd 1 Protection: Pswd 1 Read Read Read No Read No Read No Write No Write Write No Write No Write M24LR64-R sector security protection after power-up Sector security status byte b7b6b5 xxx xxx xxx xxx xxx b4 0 0 0 0 0 b3 0 1 1 1 1 b2 0 0 0 1 1 b1 0 0 1 0 1 b0 1 1 1 1 1 Table 12. M24LR64-R sector security protection after a valid presentation of password 1 Sector security status byte b7b6b5 Protection: Standard Protection: Pswd 1 Protection: Pswd 1 Protection: Pswd 1 Protection: Pswd 1 Read Read Read Read Read No Write Write Write Write No Write xxx xxx xxx xxx xxx b4 b3 b2 b1 b0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 0 1 1 1 1 1 1 Sector address 0 1 2 3 4 Doc ID 15170 Rev 10 25/128 System memory area M24LR64-R 4.3 I2C_Write_Lock bit area In the I2C mode only, it is possible to protect individual sectors against Write operations. This feature is controlled by the I2C_Write_Lock bits stored in the 8 bytes of the I2C_Write_Lock bit area starting from the location 2048 (see Table 13). Using these 64 bits, it is possible to write-protect all the 64 sectors of the M24LR64-R memory. Each bit controls the I2C write access to a specific sector as shown in Table 13. It is always possible to unprotect a sector in the I2C mode. When an I2C_Write_Lock bit is reset to 0, the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector is write-protected. In I2C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access depends on the correct presentation of the I2C password. To access the I2C_Write_Lock bit area, the device select code used for any I2C command must have the E2 Chip Enable address at 1. On delivery, the default value of the 8 bytes of the I2C_Write_Lock bit area is reset to 00h. Table 13. I2C I2C_Write_Lock bit Bits [31:24] sectors 31-24 sectors 63-56 Bits [23:16] sectors 23-16 sectors 55-48 Bits [15:8] sectors 15-8 sectors 47-40 Bits [7:0] sectors 7-0 sectors 39-32 byte address 2048 2052 E2 = 1 E2 = 1 4.4 System parameters The M24LR64-R provides the system area required by the ISO 15693 RF protocol, as shown in Table 14. The first 32-bit block starting from I2C address 2304 stores the I2C password. This password is used to activate/deactivate the write protection of the protected sector in I2C mode. At power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified. To remove the write protection, it is necessary to use the I2C Present Password described in Figure 8. When the password is correctly presented -- that is, when all the presented bits correspond to the stored ones -- it is also possible to modify the I2C password using the I2C Write Password command described in Figure 9. The next three 32-bit blocks store the three RF passwords. These passwords are neither read- nor write- accessible in the I2C mode. The next 2 bytes are used to store the AFI, at I2C location 2322, and the DSFID, at I2C location 2323. These 2 values are used during the RF Inventory sequence. They are readonly in the I2C mode. The next 8 bytes, starting from location 2324, store the 64-bit UID programmed by ST on the production line. Bytes at I2C locations 2332 to 2335 store the IC Ref and the Mem_Size data used by the RF Get_System_Info command. The UID, Mem_Size and IC Ref values are read-only data. 26/128 Doc ID 15170 Rev 10 M24LR64-R Table 14. 2 System memory area System parameter sector Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0] I C byte address E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 E2 = 1 2 2304 2308 2312 2316 2320 2324 2328 2332 DSFID (FFh) UID UID (E0h) I2C password (1) RF password 1(1) RF password 2(1) RF password 3 (1) AFI (00h) UID UID (02h) Mem_Size (03 07FFh) ST reserved UID UID ST reserved UID UID IC Ref (2Ch) 1. Delivery state: I C password= 0000 0000h, RF password = 0000 0000h, 4.5 M24LR64-R I2C password security The M24LR64-R controls I2C sector write access using the 32-bit-long I2C password and the 64-bit I2C_Write_Lock bit area. The I2C password value is managed using two I2C commands: I2C Present Password and I2C Write Password. 4.5.1 I2C Present Password command description The I2C Present Password command is used in I2C mode to present the password to the M24LR64-R in order to modify the write access rights of all the memory sectors protected by the I2C_Write_Lock bits, including the password itself. If the presented password is correct, the access rights remain activated until the M24LR64-R is powered off or until a new I2C Present Password command is issued. Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown in Figure 8, and waits for two I2C password address bytes 09h and 00h. The device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 09h, and a resend of the 4 password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes. It is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R does not start the internal comparison. When the bus master generates a Stop condition immediately after the Ack bit (during the "10th bit" time slot), an internal delay equivalent to the write cycle time is triggered. A Stop condition at any other time does not trigger the internal delay. During that delay, the M24LR64-R compares the 32 received data bits with the 32 bits of the stored I2C password. If the values match, the write access rights to all protected sectors are modified after the internal delay. If the values do not match, the protected sectors remains protected. During the internal delay, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. Doc ID 15170 Rev 10 27/128 System memory area Figure 8. I2C Present Password command Ack Device select code Start M24LR64-R Ack Password address 09h Password address 00h Ack Password [31:24] Ack Password [23:16] Ack Password [15:8] Ack Password [7:0] Ack R/W Ack Validation code 09h Password [31:24] Ack Password [23:16] Ack Password [15:8] Ack Password [7:0] Stop Ack Device select code = 1010 1 E1 E0 Ack generated during 9th bit time slot. ai15125b 4.5.2 I2C Write Password command description The I2C Write Password command is used to write a 32-bit block into the M24LR64-R I2C password system area. This command is used in I2C mode to update the I2C password value. It cannot be used to update any of the RF passwords. After the write cycle, the new I2C password value is automatically activated. The I2C password value can only be modified after issuing a valid I2C Present Password command. On delivery, the I2C default password value is set to 0000 0000h and is activated. Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown in Figure 9, and waits for the two I2C password address bytes, 09h and 00h. The device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 07h, and a resend of the 4 password data bytes. The most significant byte of the password is sent first, followed by the least significant bytes. It is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R does not modify the I2C password value. When the bus master generates a Stop condition immediately after the Ack bit (during the 10th bit time slot), the internal write cycle is triggered. A Stop condition at any other time does not trigger the internal write cycle. During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. 28/128 Doc ID 15170 Rev 10 M24LR64-R Figure 9. I2C Write Password command Ack Device select code Start System memory area Ack Password address 09h Password address 00h Ack Ack Ack Ack Ack New password [31:24] New password [23:16] New password [15:8] New password [7:0] R/W Ack Validation code 07h Ack Ack Ack Ack New password [31:24] New password [23:16] New password [15:8] New password [7:0] Stop Device select code = 1010 1 E1 E0 Ack generated during 9th bit time slot. ai15126 Doc ID 15170 Rev 10 29/128 I2C device operation M24LR64-R 5 I2C device operation The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24LR64-R device is always a slave in all communications. 5.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. 5.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal write cycle. 5.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 5.4 Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 30/128 Doc ID 15170 Rev 10 M24LR64-R I2C device operation 5.5 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit device type identifier is 1010b. Up to four memory devices can be connected on a single I2C bus. Each one is given a unique 2-bit code on the Chip Enable (E0, E1) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 15. Operating modes RW bit 1 0 Random Address Read 1 Sequential Read Byte Write Page Write 1 0 0 1 1 4 bytes 1 reStart, device select, RW = 1 Similar to Current or Random Address Read Start, device select, RW = 0 Start, device select, RW = 0 Bytes 1 Initial sequence Start, device select, RW = 1 Start, device select, RW = 0, Address Mode Current Address Read Figure 10. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited) ACK Byte Write Start Dev select R/W ACK ACK Data in Stop ACK ACK NO ACK Data in 1 Data in 2 Byte address R/W Byte address NO ACK Stop AI15115 NO ACK Byte address Byte address ACK Page Write Start NO ACK Page Write (cont'd) Dev select Data in N Doc ID 15170 Rev 10 31/128 I2C device operation M24LR64-R 5.6 Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 11, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented, does not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 10. Each data byte in the memory has a 16-bit (two byte wide) address. The most significant byte (Table 3) is sent first, followed by the least significant byte (Table 4). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal write cycle is triggered. A Stop condition at any other time slot does not trigger the internal write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device's internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. 5.7 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 11. 5.8 Page Write The Page Write mode allows up to 4 bytes to be written in a single Write cycle, provided that they are all located in the same "row" in the memory: that is, the most significant memory address bits (b12-b2) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 4 bytes of data, each of which is acknowledged by the device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the I2C_Write_Lock_bit = 1 and the I2C_password is not presented, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. 32/128 Doc ID 15170 Rev 10 M24LR64-R I2C device operation Figure 11. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) ACK Byte Write Start ACK ACK Data in ACK Dev Select R/W Byte address Byte address Stop ACK Page Write Start ACK ACK Data in 1 ACK Data in 2 ACK Data in N ACK Dev Select R/W Byte address Byte address AI15116 Figure 12. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK returned YES NO Next Operation is addressing the memory YES ReStart Send Address and Receive ACK Stop NO StartCondition YES Data for the Write cperation Ddevice select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847d Doc ID 15170 Rev 10 Stop 33/128 I2C device operation M24LR64-R 5.9 Minimizing system delays by polling on ACK During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum IC write time (tw) is shown in Table 104, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 12, is: 1. 2. 3. Initial condition: a write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 34/128 Doc ID 15170 Rev 10 M24LR64-R Figure 13. Read mode sequences ACK Current Address Read Start I2C device operation NO ACK Data out Dev select R/W ACK Random Address Read Start ACK Stop ACK Dev select * Start ACK Data out NO ACK Dev select * R/W Byte address Byte address R/W ACK Sequential Current Read Start ACK Data out 1 ACK NO ACK Data out N Stop Dev select R/W ACK Sequential Random Read Start ACK ACK Dev select * Start ACK Data out 1 R/W ACK Dev select * Byte address R/W Byte address ACK NO ACK Data out N Stop AI01105d 1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must be identical. Doc ID 15170 Rev 10 35/128 Stop I2C device operation M24LR64-R 5.10 Read operations Read operations are performed independently of the state of the I2C_Write_Lock bit. After the successful completion of a Read operation, the device's internal address counter is incremented by one, to point to the next byte address. 5.11 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 13) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 5.12 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 13, without acknowledging the byte. 5.13 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 13. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h. 5.14 Acknowledge in Read mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 36/128 Doc ID 15170 Rev 10 M24LR64-R User memory initial state 6 User memory initial state The device is delivered with all bits in the user memory array set to 1 (each byte contains FFh). 7 RF device operation The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5. Each sector can be individually read- and/or write-protected using a specific lock or password command. Read and Write operations are possible if the addressed block is not protected. During a Write, the 32 bits of the block are replaced by the new 32-bit value. The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user and its value is written by ST on the production line. The M24LR64-R also includes an AFI register in which the application family identifier is stored, and a DSFID register in which the data storage family identifier used in the anticollision algorithm is stored. The M24LR64-R has three additional 32-bit blocks in which the password codes are stored. Doc ID 15170 Rev 10 37/128 RF device operation M24LR64-R 7.1 Commands The M24LR64-R supports the following commands: Inventory, used to perform the anticollision sequence. Stay Quiet, used to put the M24LR64-R in quiet mode, where it does not respond to any inventory command. Select, used to select the M24LR64-R. After this command, the M24LR64-R processes all Read/Write commands with Select_flag set. Reset To Ready, used to put the M24LR64-R in the ready state. Read Block, used to output the 32 bits of the selected block and its locking status. Write Block, used to write the 32-bit value in the selected block, provided that it is not locked. Read Multiple Blocks, used to read the selected blocks and send back their value. Write AFI, used to write the 8-bit value in the AFI register. Lock AFI, used to lock the AFI register. Write DSFID, used to write the 8-bit value in the DSFID register. Lock DSFID, used to lock the DSFID register. Get System Info, used to provide the system information value Get Multiple Block Security Status, used to send the security status of the selected block. Initiate, used to trigger the tag response to the Inventory Initiated sequence. Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate command. Write-sector Password, used to write the 32 bits of the selected password. Lock-sector Password, used to write the Sector security status bits of the selected sector. Present-sector Password, enables the user to present a password to unprotect the user blocks linked to this password. Fast Initiate, used to trigger the tag response to the Inventory Initiated sequence. Fast Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate command. Fast Read Single Block, used to output the 32 bits of the selected block and its locking status. Fast Read Multiple Blocks, used to read the selected blocks and send back their value. 38/128 Doc ID 15170 Rev 10 M24LR64-R RF device operation 7.2 Initial dialog for vicinity cards The dialog between the vicinity coupling device or VCD (commonly the "RF reader") and the vicinity integrated circuit card or VICC (M24LR64-R) takes place as follows: activation of the M24LR64-R by the RF operating field of the VCD transmission of a command by the VCD transmission of a response by the M24LR64-R These operations use the RF power transfer and communication signal interface described below (see Power transfer, Frequency and Operating field). This technique is called RTF (Reader Talk First). 7.2.1 Power transfer Power is transferred to the M24LR64-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR64-R and the VCD. The RF operating field of the VCD is transformed on the M24LR64-R antenna to an AC Voltage which is rectified, filtered and internally regulated. The amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator. 7.2.2 Frequency The ISO 15693 standard defines the carrier frequency (fC) of the operating field as 13.56 MHz 7 kHz. 7.2.3 Operating field The M24LR64-R operates continuously between the minimum and maximum values of the electromagnetic field H defined in Table 105. The VCD has to generate a field within these limits. Doc ID 15170 Rev 10 39/128 Communication signal from VCD to M24LR64-R M24LR64-R 8 Communication signal from VCD to M24LR64-R Communications between the VCD and the M24LR64-R takes place using the modulation principle of ASK (Amplitude Shift Keying). Two modulation indexes are used, 10% and 100%. The M24LR64-R decodes both. The VCD determines which index is used. The modulation index is defined as [a - b]/[a + b] where a is the peak signal amplitude and b, the minimum signal amplitude of the carrier frequency. Depending on the choice made by the VCD, a "pause" will be created as described in Figure 14 and Figure 15. The M24LR64-R is operational for any degree of modulation index from between 10% and 30%. Figure 14. 100% modulation waveform t1 Carrier Amplitude 105% t4 t3 a 95% 60% t2 5% b t t1 t2 t3 t4 Min (s) Max (s) 9,44 6,0 2,1 t1 0 4,5 0 0,8 The clock recovery shall be operational after t4 max. ai15793 40/128 Doc ID 15170 Rev 10 M24LR64-R Table 16. Communication signal from VCD to M24LR64-R 10% modulation parameters Parameter definition 0.1 x (a - b) 0.1 x (a - b) Value max max Symbol hr hf Figure 15. 10% modulation waveform Carrier Amplitude t1 t2 t3 y hf hr a b y t t1 t2 t3 Modulation Index Min 6,0 s 3,0 s 0 10% Max 9,44 s t1 4,5 s 30% y hf, hr 0,05 (a-b) 0,1 (a-b) max The VICC shall be operational for any value of modulation index between 10 % and 30 %. ai15794 Doc ID 15170 Rev 10 41/128 Data rate and data coding M24LR64-R 9 Data rate and data coding The data coding implemented in the M24LR64-R uses pulse position modulation. Both data coding modes that are described in the ISO15693 are supported by the M24LR64-R. The selection is made by the VCD and indicated to the M24LR64-R within the start of frame (SOF). 9.1 Data coding mode: 1 out of 256 The value of one single byte is represented by the position of one pause. The position of the pause on 1 of 256 successive time periods of 18.88 s (256/fC), determines the value of the byte. In this case the transmission of one byte takes 4.833 ms and the resulting data rate is 1.65 Kbits/s (fC/8192). Figure 16 illustrates this pulse position modulation technique. In this figure, data E1h (225 decimal) is sent by the VCD to the M24LR64-R. The pause occurs during the second half of the position of the time period that determines the value, as shown in Figure 17. A pause during the first period transmits the data value 00h. A pause during the last period transmit the data value FFh (255 decimal). Figure 16. 1 out of 256 coding mode 9.44 s Pulse Modulated Carrier 18.88 s 01 2 3 .. . . . . . . .. . . . . . . . .. . . . . . . . 2 2 5 ..................... ..................... ..................... 4.833 ms 2 5 2 2 5 3 2 5 4 2 5 5 AI06656 42/128 Doc ID 15170 Rev 10 M24LR64-R Figure 17. Detail of a time period Data rate and data coding 9.44 s 18.88 s Pulse Modulated Carrier . . . . . . . 2 2 4 2 2 5 2 2 6 . . . . . . . Time Period one of 256 AI06657 9.2 Data coding mode: 1 out of 4 The value of 2 bits is represented by the position of one pause. The position of the pause on 1 of 4 successive time periods of 18.88 s (256/fC), determines the value of the 2 bits. Four successive pairs of bits form a byte, where the least significant pair of bits is transmitted first. In this case the transmission of one byte takes 302.08 s and the resulting data rate is 26.48 Kbits/s (fC/512). Figure 18 illustrates the 1 out of 4 pulse position technique and coding. Figure 19 shows the transmission of E1h (225d - 1110 0001b) by the VCD. Doc ID 15170 Rev 10 43/128 Data rate and data coding Figure 18. 1 out of 4 coding mode M24LR64-R Pulse position for "00" 9.44 s 9.44 s 75.52 s Pulse position for "01" (1=LSB) 28.32 s 9.44 s 75.52 s Pulse position for "10" (0=LSB) 47.20s 9.44 s Pulse position for "11" 75.52 s 66.08 s 75.52 s 9.44 s AI06658 Figure 19. 1 out of 4 coding example 10 00 01 11 75.52 s 75.52 s 75.52 s 75.52 s AI06659 44/128 Doc ID 15170 Rev 10 M24LR64-R Data rate and data coding 9.3 VCD to M24LR64-R frames Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are implemented using code violation. Unused options are reserved for future use. The M24LR64-R is ready to receive a new command frame from the VCD 311.5 s (t2) after sending a response frame to the VCD. The M24LR64-R takes a power-up time of 0.1 ms after being activated by the powering field. After this delay, the M24LR64-R is ready to receive a command frame from the VCD. 9.4 Start of frame (SOF) The SOF defines the data coding mode the VCD is to use for the following command frame. The SOF sequence described in Figure 20 selects the 1 out of 256 data coding mode. The SOF sequence described in Figure 21 selects the 1 out of 4 data coding mode. The EOF sequence for either coding mode is described in Figure 22. Figure 20. SOF to select 1 out of 256 data coding mode 9.44 s 9.44 s 37.76 s 37.76 s AI06661 Figure 21. SOF to select 1 out of 4 data coding mode 9.44s 9.44s 9.44s 37.76s 37.76s AI06660 Doc ID 15170 Rev 10 45/128 Data rate and data coding Figure 22. EOF for either data coding mode M24LR64-R 9.44 s 9.44 s 37.76 s AI06662 46/128 Doc ID 15170 Rev 10 M24LR64-R Communications signal from M24LR64-R to VCD 10 Communications signal from M24LR64-R to VCD The M24LR64-R has several modes defined for some parameters, owing to which it can operate in different noise environments and meet different application requirements. 10.1 Load modulation The M24LR64-R is capable of communication to the VCD via an inductive coupling area whereby the carrier is loaded to generate a subcarrier with frequency fS. The subcarrier is generated by switching a load in the M24LR64-R. The load-modulated amplitude received on the VCD antenna must be of at least 10mV when measured as described in the test methods defined in International Standard ISO10373-7. 10.2 Subcarrier The M24LR64-R supports the one-subcarrier and two-subcarrier response formats. These formats are selected by the VCD using the first bit in the protocol header. When one subcarrier is used, the frequency fS1 of the subcarrier load modulation is 423.75 kHz (fC/32). When two subcarriers are used, the frequency fS1 is 423.75 kHz (fC/32), and frequency fS2 is 484.28 kHz (fC/28). When using the two-subcarrier mode, the M24LR64-R generates a continuous phase relationship between fS1 and fS2. 10.3 Data rates The M24LR64-R can respond using the low or the high data rate format. The selection of the data rate is made by the VCD using the second bit in the protocol header. It also supports the x2 mode available on all the Fast commands. Table 17 shows the different data rates produced by the M24LR64-R using the different response format combinations. Table 17. Response data rates Data rate Standard commands Low Fast commands Standard commands High Fast commands One subcarrier 6.62 Kbit/s (fc/2048) 13.24 Kbit/s (fc/1024) 26.48 Kbit/s (fc/512) 52.97 Kbit/s (fc/256) Two subcarriers 6.67 Kbit/s (fc/2032) not applicable 26.69 Kbit/s (fc/508) not applicable Doc ID 15170 Rev 10 47/128 Bit representation and coding M24LR64-R 11 Bit representation and coding Data bits are encoded using Manchester coding, according to the following schemes. For the low data rate, same subcarrier frequency or frequencies is/are used, in this case the number of pulses is multiplied by 4 and all times will increase by this factor. For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2. 11.1 11.1.1 Bit coding using one subcarrier High data rate A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of 18.88 s as shown in Figure 23. Figure 23. Logic 0, high data rate 37.76s ai12076 For the fast commands, a logic 0 starts with 4 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of 9.44 s as shown in Figure 24. Figure 24. Logic 0, high data rate x2 18.88s ai12066 A logic 1 starts with an unmodulated time of 18.88 s followed by 8 pulses at 423.75 kHz (fC/32) as shown in Figure 25. Figure 25. Logic 1, high data rate 37.76s ai12077 For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 s followed by 4 pulses of 423.75 kHz (fC/32) as shown in Figure 26. Figure 26. Logic 1, high data rate x2 18.88s ai12067 48/128 Doc ID 15170 Rev 10 M24LR64-R Bit representation and coding 11.1.2 Low data rate A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of 75.52 s as shown in Figure 27. Figure 27. Logic 0, low data rate 151.04s ai12068 For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (fC/32) followed by an unmodulated time of 37.76 s as shown in Figure 28. Figure 28. Logic 0, low data rate x2 75.52s ai12069 A logic 1 starts with an unmodulated time of 75.52 s followed by 32 pulses at 423.75 kHz (fC/32) as shown in Figure 29. Figure 29. Logic 1, low data rate 151.04s ai12070 For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 s followed by 16 pulses at 423.75 kHz (fC/32) as shown in Figure 29. Figure 30. Logic 1, low data rate x2 75.52s ai12071 Doc ID 15170 Rev 10 49/128 Bit representation and coding M24LR64-R 11.2 11.3 Bit coding using two subcarriers High data rate A logic 0 starts with 8 pulses at 423.75 kHz (fC/32) followed by 9 pulses at 484.28 kHz (fC/28) as shown in Figure 31. For the Fast commands, the x2 mode is not available. Figure 31. Logic 0, high data rate 37.46s ai12074 A logic 1 starts with 9 pulses at 484.28 kHz (fC/28) followed by 8 pulses at 423.75 kHz (fC/32) as shown in Figure 32. For the Fast commands, the x2 mode is not available. Figure 32. Logic 1, high data rate 37.46s ai12073 11.4 Low data rate A logic 0 starts with 32 pulses at 423.75 kHz (fC/32) followed by 36 pulses at 484.28 kHz (fC/28) as shown in Figure 33. For the Fast commands, the x2 mode is not available. Figure 33. Logic 0, low data rate 149.84s ai12072 A logic 1 starts with 36 pulses at 484.28 kHz (fC/28) followed by 32 pulses at 423.75 kHz (fC/32) as shown in Figure 34. For the Fast commands, the x2 mode is not available. Figure 34. Logic 1, low data rate 149.84s ai12075 50/128 Doc ID 15170 Rev 10 M24LR64-R M24LR64-R to VCD frames 12 M24LR64-R to VCD frames Frames are delimited by an SOF and an EOF. They are implemented using code violation. Unused options are reserved for future use. For the low data rate, the same subcarrier frequency or frequencies is/are used. In this case the number of pulses is multiplied by 4. For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2. 12.1 12.2 SOF when using one subcarrier High data rate The SOF includes an unmodulated time of 56.64 s, followed by 24 pulses at 423.75 kHz (fC/32), and a logic 1 that consists of an unmodulated time of 18.88 s followed by 8 pulses at 423.75 kHz as shown in Figure 35. Figure 35. Start of frame, high data rate, one subcarrier 113.28s 37.76s ai12078 For the Fast commands, the SOF comprises an unmodulated time of 28.32 s, followed by 12 pulses at 423.75 kHz (fC/32), and a logic 1 that consists of an unmodulated time of 9.44s followed by 4 pulses at 423.75 kHz as shown in Figure 36. Figure 36. Start of frame, high data rate, one subcarrier x2 56.64s 18.88s ai12079 12.3 Low data rate The SOF comprises an unmodulated time of 226.56 s, followed by 96 pulses at 423.75 kHz (fC/32), and a logic 1 that consists of an unmodulated time of 75.52 s followed by 32 pulses at 423.75 kHz as shown in Figure 37. Figure 37. Start of frame, low data rate, one subcarrier 453.12s 151.04s ai12080 Doc ID 15170 Rev 10 51/128 M24LR64-R to VCD frames M24LR64-R For the Fast commands, the SOF comprises an unmodulated time of 113.28 s, followed by 48 pulses at 423.75 kHz (fC/32), and a logic 1 that includes an unmodulated time of 37.76 s followed by 16 pulses at 423.75 kHz as shown in Figure 38. Figure 38. Start of frame, low data rate, one subcarrier x2 226.56s 75.52s ai12081 12.4 12.5 SOF when using two subcarriers High data rate The SOF comprises 27 pulses at 484.28 kHz (fC/28), followed by 24 pulses at 423.75 kHz (fC/32), and a logic 1 that includes 9 pulses at 484.28 kHz followed by 8 pulses at 423.75 kHz as shown in Figure 39. For the Fast commands, the x2 mode is not available. Figure 39. Start of frame, high data rate, two subcarriers 112.39s 37.46s ai12082 12.6 Low data rate The SOF comprises 108 pulses at 484.28 kHz (fC/28), followed by 96 pulses at 423.75 kHz (fC/32), and a logic 1 that includes 36 pulses at 484.28 kHz followed by 32 pulses at 423.75 kHz as shown in Figure 40. For the Fast commands, the x2 mode is not available. Figure 40. Start of frame, low data rate, two subcarriers 449.56s 149.84s ai12083 52/128 Doc ID 15170 Rev 10 M24LR64-R M24LR64-R to VCD frames 12.7 12.8 EOF when using one subcarrier High data rate The EOF comprises a logic 0 that includes 8 pulses at 423.75 kHz and an unmodulated time of 18.88 s, followed by 24 pulses at 423.75 kHz (fC/32), and by an unmodulated time of 56.64 s as shown in Figure 41. Figure 41. End of frame, high data rate, one subcarriers 37.76s 113.28s ai12084 For the Fast commands, the EOF comprises a logic 0 that includes 4 pulses at 423.75 kHz and an unmodulated time of 9.44 s, followed by 12 pulses at 423.75 kHz (fC/32) and an unmodulated time of 37.76 s as shown in Figure 42. Figure 42. End of frame, high data rate, one subcarriers x2 18.88s 56.64s ai12085 12.9 Low data rate The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and an unmodulated time of 75.52 s, followed by 96 pulses at 423.75 kHz (fC/32) and an unmodulated time of 226.56 s as shown in Figure 43. Figure 43. End of frame, low data rate, one subcarriers 151.04s 453.12s ai12086 For the Fast commands, the EOF comprises a logic 0 that includes 16 pulses at 423.75 kHz and an unmodulated time of 37.76 s, followed by 48 pulses at 423.75 kHz (fC/32) and an unmodulated time of 113.28 s as shown in Figure 44. Figure 44. End of frame, low data rate, one subcarriers x2 75.52s 226.56s ai12087 Doc ID 15170 Rev 10 53/128 M24LR64-R to VCD frames M24LR64-R 12.10 12.11 EOF when using two subcarriers High data rate The EOF comprises a logic 0 that includes 8 pulses at 423.75 kHz and 9 pulses at 484.28 kHz, followed by 24 pulses at 423.75 kHz (fC/32) and 27 pulses at 484.28 kHz (fC/28) as shown in Figure 45. For the Fast commands, the x2 mode is not available. Figure 45. End of frame, high data rate, two subcarriers 37.46s 112.39s ai12088 12.12 Low data rate The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and 36 pulses at 484.28 kHz, followed by 96 pulses at 423.75 kHz (fC/32) and 108 pulses at 484.28 kHz (fC/28) as shown in Figure 46. For the Fast commands, the x2 mode is not available. Figure 46. End of frame, low data rate, two subcarriers 149.84s 449.56s ai12089 54/128 Doc ID 15170 Rev 10 M24LR64-R Unique identifier (UID) 13 Unique identifier (UID) The M24LR64-R is uniquely identified by a 64-bit unique identifier (UID). This UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and comprises: 8 MSBs with a value of E0h The IC manufacturer code of ST 02h, on 8 bits (ISO/IEC 7816-6/AM1) a unique serial number on 48 bits UID format MSB LSB 48 0x02 47 Unique serial number 0 Table 18. 63 0xE0 56 55 With the UID each M24LR64-R can be addressed uniquely and individually during the anticollision loop and for one-to-one exchanges between a VCD and an M24LR64-R. Doc ID 15170 Rev 10 55/128 Application family identifier (AFI) M24LR64-R 14 Application family identifier (AFI) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to identify, among all the M24LR64-Rs present, only the M24LR64-Rs that meet the required application criteria. Figure 47. M24LR64-R decision tree for AFI Inventory request received No AFI flag set ? Yes AFI value =0? Yes AFI value = Internal value ? Yes No No Answer given by the M24RF64 to the Inventory request No answer AI15130 The AFI is programmed by the M24LR64-R issuer (or purchaser) in the AFI register. Once programmed and Locked, it can no longer be modified. The most significant nibble of the AFI is used to code one specific or all application families. The least significant nibble of the AFI is used to code one specific or all application subfamilies. Subfamily codes different from 0 are proprietary. (See ISO 15693-3 documentation) 56/128 Doc ID 15170 Rev 10 M24LR64-R Data storage format identifier (DSFID) 15 Data storage format identifier (DSFID) The data storage format identifier indicates how the data is structured in the M24LR64-R memory. The logical organization of data can be known instantly using the DSFID. It can be programmed and locked using the Write DSFID and Lock DSFID commands. 15.1 CRC The CRC used in the M24LR64-R is calculated as per the definition in ISO/IEC 13239. The initial register contents are all ones: "FFFF". The two-byte CRC are appended to each request and response, within each frame, before the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field. Upon reception of a request from the VCD, the M24LR64-R verifies that the CRC value is valid. If it is invalid, the M24LR64-R discards the frame and does not answer to the VCD. Upon reception of a Response from the M24LR64-R, it is recommended that the VCD verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the discretion of the VCD designer. The CRC is transmitted least significant byte first. Each byte is transmitted least significant bit first. Table 19. CRC transmission rules LSByte LSBit CRC 16 (8 bits) MSBit LSBit CRC 16 (8 bits) MSByte MSBit Doc ID 15170 Rev 10 57/128 M24LR64-R protocol description M24LR64-R 16 M24LR64-R protocol description The transmission protocol (or simply protocol) defines the mechanism used to exchange instructions and data between the VCD and the M24LR64-R, in both directions. It is based on the concept of "VCD talks first". This means that an M24LR64-R will not start transmitting unless it has received and properly decoded an instruction sent by the VCD. The protocol is based on an exchange of: a request from the VCD to the M24LR64-R a response from the M24LR64-R to the VCD Each request and each response are contained in a frame. The frame delimiters (SOF, EOF) are described in Section 12: M24LR64-R to VCD frames. Each request consists of: a request SOF (see Figure 20 and Figure 21) flags a command code parameters, depending on the command application data a 2-byte CRC a request EOF (see Figure 22) an answer SOF (see Figure 35 to Figure 40) flags parameters, depending on the command application data a 2-byte CRC an answer EOF (see Figure 41 to Figure 46) Each response consists of: The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight (8), that is an integer number of bytes. A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is transmitted least significant byte (LSByte) first, each byte is transmitted least significant bit (LSBit) first. The setting of the flags indicates the presence of the optional fields. When the flag is set (to one), the field is present. When the flag is reset (to zero), the field is absent. Table 20. VCD request frame format Command code Parameters Data 2-byte CRC Request EOF Request SOF Request_flags Table 21. Response SOF M24LR64-R Response frame format Response_flags Parameters Data 2-byte CRC Response EOF 58/128 Doc ID 15170 Rev 10 M24LR64-R Figure 48. M24LR64-R protocol timing M24LR64-R protocol description VCD Request frame (Table 20) Response frame (Table 21) Request frame (Table 20) Response frame (Table 21) M24LR64 -R Timing <-t1-> <-t2-> <-t1-> <-t2-> Doc ID 15170 Rev 10 59/128 M24LR64-R states M24LR64-R 17 M24LR64-R states An M24LR64-R can be in one of 4 states: Power-off Ready Quiet Selected Transitions between these states are specified in Figure 49: M24LR64-R state transition diagram and Table 22: M24LR64-R response depending on Request_flags. 17.1 Power-off state The M24LR64-R is in the Power-off state when it does not receive enough energy from the VCD. 17.2 Ready state The M24LR64-R is in the Ready state when it receives enough energy from the VCD. When in the Ready state, the M24LR64-R answers any request where the Select_flag is not set. 17.3 Quiet state When in the Quiet state, the M24LR64-R answers any request except for Inventory requests with the Address_flag set. 17.4 Selected state In the Selected state, the M24LR64-R answers any request in all modes (see Section 18: Modes): Request in Select mode with the Select_flag set Request in Addressed mode if the UID matches Request in Non-Addressed mode as it is the mode for general requests 60/128 Doc ID 15170 Rev 10 M24LR64-R Table 22. M24LR64-R response depending on Request_flags Address_flag Flags 1 Addressed 0 Non addressed X X X X X X M24LR64-R states Select_flag 1 Selected 0 Non selected X M24LR64-R in Ready or Selected state (Devices in Quiet state do not answer) M24LR64-R in Selected state M24LR64-R in Ready, Quiet or Selected state (the device which matches the UID) Error (03h) X Figure 49. M24LR64-R state transition diagram 1. The M24LR64-R returns to the "Power Off" state only when both conditions are met: the VCC pin is not supplied (0 V or HiZ) and the tag is out of the RF field. Please refer to application note AN3057 for more information. 2. The intention of the state transition method is that only one M24LR64-R should be in the selected state at a time. Doc ID 15170 Rev 10 61/128 Modes M24LR64-R 18 Modes The term "mode" refers to the mechanism used in a request to specify the set of M24LR64Rs that will answer the request. 18.1 Addressed mode When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID (UID) of the addressed M24LR64-R. Any M24LR64-R that receives a request with the Address_flag set to 1 compares the received Unique ID to its own. If it matches, then the M24LR64-R executes the request (if possible) and returns a response to the VCD as specified in the command description. If the UID does not match, then it remains silent. 18.2 Non-addressed mode (general request) When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain a Unique ID. Any M24LR64-R receiving a request with the Address_flag cleared to 0 executes it and returns a response to the VCD as specified in the command description. 18.3 Select mode When the Select_flag is set to 1 (Select mode), the request does not contain an M24LR64R Unique ID. The M24LR64-R in the Selected state that receives a request with the Select_flag set to 1 executes it and returns a response to the VCD as specified in the command description. Only M24LR64-Rs in the Selected state answer a request where the Select_flag set to 1. The system design ensures in theory that only one M24LR64-R can be in the Select state at a time. 62/128 Doc ID 15170 Rev 10 M24LR64-R Request format 19 Request format The request consists of: an SOF flags a command code parameters and data a CRC an EOF General request format Command code Parameters Data CRC E O F Table 23. S O F Request_flags 19.1 Request flags In a request, the "flags" field specifies the actions to be performed by the M24LR64-R and whether corresponding fields are present or not. The flags field consists of eight bits. The bit 3 (Inventory_flag) of the request flag defines the contents of the 4 MSBs (bits 5 to 8). When bit 3 is reset (0), bits 5 to 8 define the M24LR64R selection criteria. When bit 3 is set (1), bits 5 to 8 define the M24LR64-R Inventory parameters. Table 24. Bit No Bit 1 Definition of request flags 1 to 4 Flag Level 0 1 Description A single subcarrier frequency is used by the M24LR64-R Two subcarrier are used by the M24LR64-R Low data rate is used High data rate is used The meaning of flags 5 to 8 is described in Table 25 The meaning of flags 5 to 8 is described in Table 26 No Protocol format extension Protocol format extension Subcarrier_flag(1) Bit 2 Data_rate_flag(2) 0 1 0 Bit 3 Inventory_flag 1 0 Bit 4 Protocol_extension_flag 1 1. Subcarrier_flag refers to the M24LR64-R-to-VCD communication. 2. Data_rate_flag refers to the M24LR64-R-to-VCD communication Doc ID 15170 Rev 10 63/128 Request format Table 25. Bit No . M24LR64-R Request flags 5 to 8 when Bit 3 = 0 Flag Select flag(1) Level 0 1 0 Description Request is executed by any M24LR64-R according to the setting of Address_flag Request is executed only by the M24LR64-R in Selected state Request is not addressed. UID field is not present. The request is executed by all M24LR64-Rs. Request is addressed. UID field is present. The request is executed only by the M24LR64-R whose UID matches the UID specified in the request. Option not activated. Option activated. Bit 5 Bit 6 Address flag(1) 1 0 Bit 7 Bit 8 Option flag 1 RFU 0 1. If the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the request. Table 26. Bit No Bit 5 Request flags 5 to 8 when Bit 3 = 1 Flag AFI flag 1 0 AFI field is present 16 slots 1 slot Level 0 AFI field is not present Description Bit 6 Bit 7 Bit 8 Nb_slots flag 1 Option flag RFU 0 0 64/128 Doc ID 15170 Rev 10 M24LR64-R Response format 20 Response format The response consists of: an SOF flags parameters and data a CRC an EOF General response format Response_flags Parameters Data CRC E O F Table 27. S O F 20.1 Response flags In a response, the flags indicate how actions have been performed by the M24LR64-R and whether corresponding fields are present or not. The response flags consist of eight bits. Table 28. Bit No Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Definitions of response flags 1 to 8 Flag Error_flag 1 RFU RFU Extension flag RFU RFU RFU RFU 0 0 0 0 0 0 0 No extension Error detected. Error code is in the "Error" field. Level 0 No error Description Doc ID 15170 Rev 10 65/128 Response format M24LR64-R 20.2 Response error code If the Error_flag is set by the M24LR64-R in the response, the Error code field is present and provides information about the error that occurred. Error codes not specified in Table 29 are reserved for future use. Table 29. Response error code definition Meaning The command is not recognized, for example a format error occurred The option is not supported Error with no information given The specified block is not available The specified block is already locked and thus cannot be locked again The specified block is locked and its contents cannot be changed. The specified block was not successfully programmed The specified block was not successfully locked The specified block is read-protected Error code 02h 03h 0Fh 10h 11h 12h 13h 14h 15h 66/128 Doc ID 15170 Rev 10 M24LR64-R Anticollision 21 Anticollision The purpose of the anticollision sequence is to inventory the M24LR64-Rs present in the VCD field using their unique ID (UID). The VCD is the master of communications with one or several M24LR64-Rs. It initiates M24LR64-R communication by issuing the Inventory request. The M24LR64-R sends its response in the determined slot or does not respond. 21.1 Request parameters When issuing the Inventory Command, the VCD: sets the Nb_slots_flag as desired adds the mask length and the mask value after the command field The mask length is the number of significant bits of the mask value. The mask value is contained in an integer number of bytes. The mask length indicates the number of significant bits. LSB is transmitted first If the mask length is not a multiple of 8 (bits), as many 0-bits as required will be added to the mask value MSB so that the mask value is contained in an integer number of bytes The next field starts at the next byte boundary. Inventory request format LSB Request_ Command flags 8 bits 8 bits Optional AFI 8 bits Mask length 8 bits Mask value 0 to 8 bytes CRC 16 bits EOF Table 30. MSB SOF In the example of the Table 31 and Figure 50, the mask length is 11 bits. Five 0-bits are added to the mask value MSB. The 11-bit Mask and the current slot number are compared to the UID. Table 31. Example of the addition of 0-bits to an 11-bit mask value LSB (b0) 100 1100 1111 11-bit mask value (b15) MSB 0000 0 0-bits added Doc ID 15170 Rev 10 67/128 Anticollision M24LR64-R Figure 50. Principle of comparison between the mask, the slot number and the UID MSB LSB 0000 0100 1100 1111 b 16 bits MSB LSB 100 1100 1111 b 11 bits Mask value received in the Inventory command The Mask value less the padding 0s is loaded into the Tag comparator The Slot counter is calculated Nb_slots_flags = 0 (16 slots), Slot Counter is 4 bits MSB LSB xxxx 4 bits The Slot counter is concatened to the Mask value Nb_slots_flags = 0 MSB LSB xxxx 100 1100 1111 b 15 bits The concatenated result is compared with the least significant bits of the Tag UID. UID b63 b0 xxxx xxxx ..... xxxx xxxx x xxx xxxx xxxx xxxx b Bits ignored Compare 64 bits AI06682 The AFI field is present if the AFI_flag is set. The pulse is generated according to the definition of the EOF in ISO/IEC 15693-2. The first slot starts immediately after the reception of the request EOF. To switch to the next slot, the VCD sends an EOF. The following rules and restrictions apply: if no M24LR64-R answer is detected, the VCD may switch to the next slot by sending an EOF, if one or more M24LR64-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot. 68/128 Doc ID 15170 Rev 10 M24LR64-R Request processing by the M24LR64-R 22 Request processing by the M24LR64-R Upon reception of a valid request, the M24LR64-R performs the following algorithm: NbS is the total number of slots (1 or 16) SN is the current slot number (0 to 15) LSB (value, n) function returns the n Less Significant Bits of value MSB (value, n) function returns the n Most Significant Bits of value "&" is the concatenation operator Slot_Frame is either an SOF or an EOF SN = 0 if (Nb_slots_flag) then NbS = 1 SN_length = 0 endif else NbS = 16 SN_length = 4 endif label1: if LSB(UID, SN_length + Mask_length) = LSB(SN,SN_length)&LSB(Mask,Mask_length) then answer to inventory request endif wait (Slot_Frame) if Slot_Frame = SOF then Stop Anticollision decode/process request exit endif if Slot_Frame = EOF if SN < NbS-1 then SN = SN + 1 goto label1 exit endif endif Doc ID 15170 Rev 10 69/128 Explanation of the possible cases M24LR64-R 23 Explanation of the possible cases Figure 51 summarizes the main possible cases that can occur during an anticollision sequence when the slot number is 16. The different steps are: The VCD sends an Inventory request, in a frame terminated by an EOF. The number of slots is 16. M24LR64-R_1 transmits its response in Slot 0. It is the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD; The VCD sends an EOF in order to switch to the next slot. In slot 1, two M24LR64-Rs, M24LR64-R_2 and M24LR64-R_3 transmit a response, thus generating a collision. The VCD records the event and remembers that a collision was detected in Slot 1. The VCD sends an EOF in order to switch to the next slot. In Slot 2, no M24LR64-R transmits a response. Therefore the VCD does not detect any M24LR64-R SOF and decides to switch to the next slot by sending an EOF. In slot 3, there is another collision caused by responses from M24LR64-R_4 and M24LR64-R_5 The VCD then decides to send a request (for instance a Read Block) to M24LR64-R_1 whose UID has already been correctly received. All M24LR64-Rs detect an SOF and exit the anticollision sequence. They process this request and since the request is addressed to M24LR64-R_1, only M24LR64-R_1 transmits a response. All M24LR64-Rs are ready to receive another request. If it is an Inventory command, the slot numbering sequence restarts from 0. Note: The decision to interrupt the anticollision sequence is made by the VCD. It could have continued to send EOFs until Slot 16 and only then sent the request to M24LR64-R_1. 70/128 Doc ID 15170 Rev 10 M24LR64-R Slot 0 Slot 1 Slot 2 Slot 3 VCD SOF Inventory EOF Request EOF EOF EOF Response 2 SOF Request to EOF M24RF64_1 Response 4 Figure 51. Description of a possible anticollision sequence Doc ID 15170 Rev 10 M24RF64s Response 1 Response 3 Timing t1 t2 t1 t2 t3 t1 Comment No collision Collision No Response Time Response from M24RF64_1 Response 5 t2 t1 Collision Explanation of the possible cases AI15117 71/128 Inventory Initiated command M24LR64-R 24 Inventory Initiated command The M24LR64-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer to Inventory Initiated commands. For applications in which multiple tags are moving in front of a reader, it is possible to miss tags using the standard inventory command. The reason is that the inventory sequence has to be performed on a global tree search. For example, a tag with a particular UID value may have to wait the run of a long tree search before being inventoried. If the delay is too long, the tag may be out of the field before it has been detected. Using the Initiate command, the inventory sequence is optimized. When multiple tags are moving in front of a reader, the ones which are within the reader field will be initiated by the Initiate command. In this case, a small batch of tags will answer to the Inventory Initiated command which will optimize the time necessary to identify all the tags. When finished, the reader has to issue a new Initiate command in order to initiate a new small batch of tags which are new inside the reader field. It is also possible to reduce the inventory sequence time using the Fast Initiate and Fast Inventory Initiated commands. These commands allow the M24LR64-Rs to increase their response data rate by a factor of 2, up to 53 Kbit/s. 72/128 Doc ID 15170 Rev 10 M24LR64-R Timing definition 25 25.1 Timing definition t1: M24LR64-R response delay Upon detection of the rising edge of the EOF received from the VCD, the M24LR64-R waits for a time t1nom before transmitting its response to a VCD request or before switching to the next slot during an inventory process. Values of t1 are given in Table 32. The EOF is defined in Figure 22 on page 46. 25.2 t2: VCD new request delay t2 is the time after which the VCD may send an EOF to switch to the next slot when one or more M24LR64-R responses have been received during an Inventory command. It starts from the reception of the EOF from the M24LR64-Rs. The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR64-R. t2 is also the time after which the VCD may send a new request to the M24LR64-R as described in Table 48: M24LR64-R protocol timing. Values of t2 are given in Table 32. 25.3 t3: VCD new request delay in the absence of a response from the M24LR64-R t3 is the time after which the VCD may send an EOF to switch to the next slot when no M24LR64-R response has been received. The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR64-R. From the time the VCD has generated the rising edge of an EOF: If this EOF is 100% modulated, the VCD waits a time at least equal to t3min before sending a new EOF. If this EOF is 10% modulated, the VCD waits a time at least equal to the sum of t3min + the M24LR64-R nominal response time (which depends on the M24LR64-R data rate and subcarrier modulation mode) before sending a new EOF. Timing values(1) Minimum (min) values t1 t2 t3 318.6 s 309.2 s t1max (2) Table 32. Nominal (nom) values 320.9 s No tnom No tnom Maximum (max) values 323.3 s No tmax No tmax + tSOF(3) 1. The tolerance of specific timings is 32/fC. 2. t1max does not apply for write alike requests. Timing conditions for write alike requests are defined in the command description. 3. tSOF is the time taken by the M24LR64-R to transmit an SOF to the VCD. tSOF depends on the current data rate: High data rate or Low data rate. Doc ID 15170 Rev 10 73/128 Commands codes M24LR64-R 26 Commands codes The M24LR64-R supports the commands described in this section. Their codes are given in Table 33. Table 33. Command codes Function Inventory Stay Quiet Read Single Block Write Single Block Read Multiple Block Select Reset to Ready Write AFI Lock AFI Write DSFID Lock DSFID Get System Info Command code custom 2Ch B1h B2h B3h C0h C1h C2h C3h D1h D2h Function Get Multiple Block Security Status Write-sector Password Lock-sector Password Present-sector Password Fast Read Single Block Fast Inventory Initiated Fast Initiate Fast Read Multiple Block Inventory Initiated Initiate Command code standard 01h 02h 20h 21h 23h 25h 26h 27h 28h 29h 2Ah 2Bh 74/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.1 Inventory When receiving the Inventory request, the M24LR64-R runs the anticollision sequence. The Inventory_flag is set to 1. The meaning of flags 5 to 8 is shown in Table 26: Request flags 5 to 8 when Bit 3 = 1. The request contains: the flags, the Inventory command code (see Table 33: Command codes) the AFI if the AFI flag is set the mask length the mask value the CRC The M24LR64-R does not generate any answer in case of error. Table 34. Inventory request format Optional AFI 8 bits Mask length 8 bits Mask value 0 - 64 bits CRC16 16 bits Request EOF Request Request_flags Inventory SOF 8 bits 01h The response contains: the flags the Unique ID Inventory response format DSFID 8 bits UID 64 bits CRC16 16 bits Response EOF Table 35. Response Response_ SOF flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value of t3 is: t3min = 4384/fC (323.3s) + tSOF If the VCD sends a 10% modulated EOF, the minimum value of t3 is: t3min = 4384/fC (323.3s) + tNRT tSOF is the time required by the M24LR64-R to transmit an SOF to the VCD tNRT is the nominal response time of the M24LR64-R where: tNRT and tSOF are dependent on the M24LR64-R-to-VCD data rate and subcarrier modulation mode. Doc ID 15170 Rev 10 75/128 Commands codes M24LR64-R 26.2 Stay Quiet Command code = 0x02 On receiving the Stay Quiet command, the M24LR64-R enters the Quiet State if no error occurs, and does NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs. When in the Quiet state: the M24LR64-R does not process any request if the Inventory_flag is set, the M24LR64-R processes any Addressed request it is reset (power off), receiving a Select request. It then goes to the Selected state, receiving a Reset to Ready request. It then goes to the Ready state. Stay Quiet request format Request flags 8 bits Stay Quiet 02h UID 64 bits CRC16 16 bits Request EOF The M24LR64-R exits the Quiet State when: Table 36. Request SOF The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset to 0 and Address_flag is set to 1). Figure 52. Stay Quiet frame exchange between VCD and M24LR64-R VCD M24LR64-R Timing SOF Stay Quiet request EOF 76/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.3 Read Single Block On receiving the Read Single Block command, the M24LR64-R reads the requested block and sends back its 32-bit value in the response. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. The Option_flag is supported. Table 37. Read Single Block request format UID(1) 64 bits Block number 16 bits CRC16 16 bits Request EOF Request Request_ Read Single SOF flags Block 8 bits 20h 1. Gray means that the field is optional. Request parameters: Option_flag UID (optional) Block number Read Single Block response format when Error_flag is NOT set Response_flags 8 bits Sector security status(1) 8 bits Data 32 bits CRC16 16 bits Response EOF Table 38. Response SOF 1. Gray means that the field is optional. Response parameters: Sector security status if Option_flag is set (see Table 39: Sector security status) 4 bytes of block data Sector security status b6 b5 b4 b3 b2 b1 b0 0: Current sector not locked 1: Current sector locked password control bits Read / Write protection bits Table 39. b7 Reserved for future use. All at 0 Table 40. Response SOF Read Single Block response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Doc ID 15170 Rev 10 77/128 Commands codes Response parameter: M24LR64-R Error code as Error_flag is set - - - - 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available 15h: the specified block is read-protected Figure 53. Read Single Block frame exchange between VCD and M24LR64-R Read Single Block request VCD M24LR64R SOF EOF <-t1-> SOF Read Single Block response EOF 78/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.4 Write Single Block On receiving the Write Single Block command, the M24LR64-R writes the data contained in the request to the requested block and reports whether the write operation was successful in the response. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). Otherwise, the M24LR64-R may not program correctly the data into the memory. The Wt time is equal to t1nom + 18 x 302 s. Table 41. Write Single Block request format Write Single Block 21h UID(1) 64 bits Block number 16 bits Data 32 bits CRC16 16 bits Request EOF Request Request_ SOF flags 8 bits 1. Gray means that the field is optional. Request parameters: UID (optional) Block number Data Write Single Block response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 42. Response SOF Response parameter: No parameter. The response is send back after the writing cycle. Write Single Block response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 43. Response SOF Response parameter: Error code as Error_flag is set: - - - - - 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available 12h: the specified block is locked and its contents cannot be changed. 13h: the specified block was not successfully programmed Doc ID 15170 Rev 10 79/128 Commands codes Figure 54. Write Single Block frame exchange between VCD and M24LR64-R Write Single Block request M24LR64-R VCD M24LR64-R SOF EOF <-t1-> SOF Write Single Block response EOF Write sequence when error M24LR64-R <------------------- Wt ---------------> SOF Write Single Block response EOF 80/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.5 Read Multiple Block When receiving the Read Multiple Block command, the M24LR64-R reads the selected blocks and sends back their value in multiples of 32 bits in the response. The blocks are numbered from '00h to '7FFh' in the request and the value is minus one (-1) in the field. For example, if the "number of blocks" field contains the value 06h, 7 blocks are read. The maximum number of blocks is fixed at 32 assuming that they are all located in the same sector. If the number of blocks overlaps sectors, the M24LR64-R returns an error code. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. The Option_flag is supported. Table 44. Read Multiple Block request format UID(1) 64 bits First block number 16 bits Number of blocks 8 bits CRC16 16 bits Request EOF Read Request Request_ Multiple SOF flags Block 8 bits 23h 1. Gray means that the field is optional. Request parameters: Option_flag UID (optional) First block number Number of blocks Read Multiple Block response format when Error_flag is NOT set Sector security status(1) 8 bits(2) Data 32 bits(2) CRC16 16 bits Response EOF Table 45. Response Response_ SOF flags 8 bits 1. Gray means that the field is optional. 2. Repeated as needed. Response parameters: Sector security status if Option_flag is set (see Table 46: Sector security status) N blocks of data Sector security status b6 b5 b4 b3 b2 b1 b0 0: Current sector not locked 1: Current sector locked password control bits Read / Write protection bits Table 46. b7 Reserved for future use. All at 0 Doc ID 15170 Rev 10 81/128 Commands codes Table 47. Read Multiple Block response format when Error_flag is set Response_flags 8 bits Error code 8 bits CRC16 16 bits M24LR64-R Response SOF Response EOF Response parameter: Error code as Error_flag is set: - - - - 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available 15h: the specified block is read-protected Figure 55. Read Multiple Block frame exchange between VCD and M24LR64-R Read Multiple EOF Block request <-t1-> SOF Read Multiple EOF Block response VCD M24LR64-R SOF 82/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.6 Select When receiving the Select command: if the UID is equal to its own UID, the M24LR64-R enters or stays in the Selected state and sends a response. if the UID does not match its own, the selected M24LR64-R returns to the Ready state and does not send a response. The M24LR64-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. If an error occurs, the M24LR64-R remains in its current state. Table 48. Select request format Select 25h UID 64 bits CRC16 16 bits Request EOF Request Request_ SOF flags 8 bits Request parameter: UID Select Block response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 49. Response SOF Response parameter: No parameter. Select response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 50. Response SOF Response parameter: Error code as Error_flag is set: - - 03h: the option is not supported 0Fh: error with no information given Figure 56. Select frame exchange between VCD and M24LR64-R VCD M24LR64 -R SOF Select request EOF <-t1-> SOF Select response EOF Doc ID 15170 Rev 10 83/128 Commands codes M24LR64-R 26.7 Reset to Ready On receiving a Reset to Ready command, the M24LR64-R returns to the Ready state if no error occurs. In the Addressed mode, the M24LR64-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. Table 51. Reset to Ready request format UID(1) 64 bits CRC16 16 bits Request EOF Request Request_ Reset to SOF flags Ready 8 bits 26h 1. Gray means that the field is optional. Request parameter: UID (optional) Reset to Ready response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 52. Response SOF Response parameter: No parameter Reset to ready response format when Error_flag is set Error code 8 bits CRC16 16 bits Response EOF Table 53. Response Response_flags SOF 8 bits Response parameter: Error code as Error_flag is set: - - 03h: the option is not supported 0Fh: error with no information given Figure 57. Reset to Ready frame exchange between VCD and M24LR64-R VCD SOF Reset to Ready request EOF Reset to Ready response M24LR64R <-t1-> SOF EOF 84/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.8 Write AFI On receiving the Write AFI request, the M24LR64-R programs the 8-bit AFI value to its memory. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). Otherwise, the M24LR64-R may not write correctly the AFI value into the memory. The Wt time is equal to t1nom + 18 x 302 s. Table 54. Write AFI request format UID(1) 64 bits AFI 8 bits CRC16 16 bits Request EOF Request Request Write SOF _flags AFI 8 bits 27h 1. Gray means that the field is optional. Request parameter: UID (optional) AFI Write AFI response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 55. Response SOF Response parameter: No parameter. Write AFI response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 56. Response SOF Response parameter: Error code as Error_flag is set - - - - 03h: the option is not supported 0Fh: error with no information given 12h: the specified block is locked and its contents cannot be changed. 13h: the specified block was not successfully programmed Doc ID 15170 Rev 10 85/128 Commands codes Figure 58. Write AFI frame exchange between VCD and M24LR64-R M24LR64-R VCD M24LR64-R SOF Write AFI request EOF <-t1-> SOF Write AFI response EOF Write sequence when error M24LR64-R <------------------ Wt --------------> SOF Write AFI EOF response 86/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.9 Lock AFI On receiving the Lock AFI request, the M24LR64-R locks the AFI value permanently. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). Otherwise, the M24LR64-R may not Lock correctly the AFI value in memory. The Wt time is equal to t1nom + 18 x 302 s. Table 57. Lock AFI request format Lock AFI 28h UID(1) 64 bits CRC16 16 bits Request EOF Request Request_ SOF flags 8 bits 1. Gray means that the field is optional. Request parameter: UID (optional) Lock AFI response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 58. Response SOF Response parameter: No parameter Lock AFI response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 59. Response SOF Response parameter: Error code as Error_flag is set - - - - 03h: the option is not supported 0Fh: error with no information given 11h: the specified block is already locked and thus cannot be locked again 14h: the specified block was not successfully locked Doc ID 15170 Rev 10 87/128 Commands codes Figure 59. Lock AFI frame exchange between VCD and M24LR64-R Lock AFI EOF request <-t1-> SOF Lock AFI response EOF M24LR64-R VCD M24LR64-R SOF Lock sequence when error M24LR64-R <----------------- Wt -------------> SOF Lock AFI response EOF 88/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.10 Write DSFID On receiving the Write DSFID request, the M24LR64-R programs the 8-bit DSFID value to its memory. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). Otherwise, the M24LR64-R may not write correctly the DSFID value in memory. The Wt time is equal to t1nom + 18 x 302 s. Table 60. Write DSFID request format UID(1) 64 bits DSFID 8 bits CRC16 16 bits Request EOF Request Request_ Write SOF flags DSFID 8 bits 29h 1. Gray means that the field is optional. Request parameter: UID (optional) DSFID Write DSFID response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 61. Response SOF Response parameter: No parameter Write DSFID response format when Error_flag is set Error code 8 bits CRC16 16 bits Response EOF Table 62. Response Response_flags SOF 8 bits Response parameter: Error code as Error_flag is set - - - - 03h: the option is not supported 0Fh: error with no information given 12h: the specified block is locked and its contents cannot be changed. 13h: the specified block was not successfully programmed Doc ID 15170 Rev 10 89/128 Commands codes Figure 60. Write DSFID frame exchange between VCD and M24LR64-R M24LR64-R VCD M24LR64-R SOF Write DSFID EOF request <-t1-> SOF Write DSFID response EOF Write sequence when error M24LR64-R <---------------- Wt ------------> SOF Write DSFID EOF response 90/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.11 Lock DSFID On receiving the Lock DSFID request, the M24LR64-R locks the DSFID value permanently. The Option_flag is supported. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%). Otherwise, the M24LR64-R may not lock correctly the DSFID value in memory. The Wt time is equal to t1nom + 18 x 302 s. Table 63. Lock DSFID request format Lock DSFID 2Ah UID(1) 64 bits CRC16 16 bits Request EOF Request Request_ SOF flags 8 bits 1. Gray means that the field is optional. Request parameter: UID (optional) Lock DSFID response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 64. Response SOF Response parameter: No parameter. Lock DSFID response format when Error_flag is set Error code 8 bits CRC16 16 bits Response EOF Table 65. Response Response_flags SOF 8 bits Response parameter: Error code as Error_flag is set: - - - - 03h: the option is not supported 0Fh: error with no information given 11h: the specified block is already locked and thus cannot be locked again 14h: the specified block was not successfully locked Doc ID 15170 Rev 10 91/128 Commands codes Figure 61. Lock DSFID frame exchange between VCD and M24LR64-R M24LR64-R VCD M24LR64-R SOF Lock DSFID EOF request <-t1-> SOF Lock DSFID response EOF Lock sequence when error M24LR64-R <----------------- Wt -------------> SOF Lock DSFID response EOF 92/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.12 Get System Info When receiving the Get System Info command, the M24LR64-R sends back its information data in the response.The Option_flag is supported and must be reset to 0. The Get System Info can be issued in both Addressed and Non Addressed modes. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. Table 66. Get System Info request format UID(1) 64 bits CRC16 16 bits Request EOF Request Request Get System SOF _flags Info 8 bits 2Bh 1. Gray means that the field is optional. Request parameter: UID (optional) Get System Info response format when Error_flag is NOT set UID 64 bits DSFID AFI Memory IC Response CRC16 Size reference EOF 2Ch 16 bits Table 67. Response Response Information SOF _flags flags 00h 0Fh 8 bits 8 bits 0307FFh Response parameters: Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are present UID code on 64 bits DSFID value AFI value Memory size. The M24LR64-R provides 2048 blocks (07FFh) of 4 byte (03h) IC reference. Only the 6 MSB are significant. Get System Info response format when Error_flag is set Response_flags 01h Error code 8 bits CRC16 16 bits Response EOF Table 68. Response SOF Response parameter: Error code as Error_flag is set: - - 03h: Option not supported 0Fh: other error Doc ID 15170 Rev 10 93/128 Commands codes M24LR64-R Figure 62. Get System Info frame exchange between VCD and M24LR64-R Get System Info request VCD M24LR64 -R SOF EOF <-t1-> SOF Get System Info response EOF 94/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.13 Get Multiple Block Security Status When receiving the Get Multiple Block Security Status command, the M24LR64-R sends back the sector security status. The blocks are numbered from '00h to '07FFh' in the request and the value is minus one (-1) in the field. For example, a value of '06' in the "Number of blocks" field requests to return the security status of 7 blocks. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. During the M24LR64-R response, if the internal block address counter reaches 07FFh, it rolls over to 0000h and the Sector Security Status bytes for that location are sent back to the reader. Table 69. Get Multiple Block Security Status request format First Number Request block CRC16 of blocks EOF number 16 bits 16 bits 16 bits Get Multiple Request Request Block SOF _flags Security Status 8 bits 2Ch UID(1) 64 bits 1. Gray means that the field is optional. Request parameter: UID (optional) First block number Number of blocks Get Multiple Block Security Status response format when Error_flag is NOT set Response_ flags 8 bits Sector security status 8 bits(1) CRC16 16 bits Response EOF Table 70. Response SOF 1. Repeated as needed. Response parameters: Sector security status (see Table 71: Sector security status) Sector security status b6 b5 b4 b3 b2 b1 b0 0: Current sector not locked 1: Current sector locked password control bits Read / Write protection bits Table 71. b7 Reserved for future use. All at 0 Doc ID 15170 Rev 10 95/128 Commands codes Table 72. Response SOF M24LR64-R Get Multiple Block Security Status response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Response parameter: Error code as Error_flag is set: - - - 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available Figure 63. Get Multiple Block Security Status frame exchange between VCD and M24LR64-R VCD M24LR64 -R SOF Get Multiple Block Security Status EOF <-t1-> SOF Get Multiple Block EOF Security Status 96/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.14 Write-sector Password On receiving the Write-sector Password command, the M24LR64-R uses the data contained in the request to write the password and reports whether the operation was successful in the response. The Option_flag is supported. During the RF write cycle time, Wt, there must be no modulation at all (neither 100% nor 10%). Otherwise, the M24LR64-R may not correctly program the data into the memory. The Wt time is equal to t1nom + 18 x 302 s. After a successful write, the new value of the selected password is automatically activated. It is not required to present the new password value until M24LR64-R power-down. Table 73. Write-sector Password request format WriteIC Mfg sector code Password B1h 02h UID(1) 64 bits Password number 8 bits Data 32 bits CRC16 16 bits Request EOF Request Request SOF _flags 8 bits 1. Gray means that the field is optional. Request parameter: UID (optional) Password number (01h = Pswd1, 02h = Pswd2, 03h = Pswd3, other = Error) Data Write-sector Password response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 74. Response SOF Response parameter: 32-bit password value. The response is sent back after the write cycle. Write-sector Password response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 75. Response SOF Response parameter: Error code as Error_flag is set: - - - - - - 02h: the command is not recognized, for example: a format error occurred 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available 12h: the specified block is locked and its contents cannot be changed. 13h: the specified block was not successfully programmed Doc ID 15170 Rev 10 97/128 Commands codes M24LR64-R Figure 64. Write-sector Password frame exchange between VCD and M24LR64-R VCD SOF Writesector Password request EOF M24LR64-R <-t1-> SOF Write-sector Password response EOF Write sequence when error M24LR64-R <----------------- Wt -------------> SOF Writesector Password response EOF 98/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.15 Lock-sector Password On receiving the Lock-sector Password command, the M24LR64-R sets the access rights and permanently locks the selected sector. The Option_flag is supported. A sector is selected by giving the address of one of its blocks in the Lock-sector Password request (Sector number field). For example, addresses 0 to 31 are used to select sector 0 and addresses 32 to 63 are used to select sector 1. Care must be taken when issuing the Lock-sector Password command as all the blocks belonging to the same sector are automatically locked by a single command. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. During the RF write cycle Wt, there should be no modulation (neither 100% nor 10%) otherwise, the M24LR64-R may not correctly lock the memory block. The Wt time is equal to t1nom + 18 x 302 s. Table 76. Lock-sector Password request format LockIC sector Mfg Password code B2h 02h UID(1) 64 bits Sector Sector Request security CRC16 number EOF status 16 bits 8 bits 16 bits Request Request SOF _flags 8 bits 1. Gray means that the field is optional. Request parameters: (optional) UID Sector number Sector security status (refer to Table 77) Sector security status b6 0 b5 0 b4 b3 b2 b1 b0 1 Read / Write protection bits Table 77. b7 0 password control bits Table 78. Response SOF Lock-sector Password response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Response parameter: No parameter. Lock-sector Password response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 79. Response SOF Doc ID 15170 Rev 10 99/128 Commands codes Response parameter: M24LR64-R Error code as Error_flag is set: - - - - - - 02h: the command is not recognized, for example: a format error occurred 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available 11h: the specified block is already locked and thus cannot be locked again 14h: the specified block was not successfully locked Figure 65. Lock-sector Password frame exchange between VCD and M24LR64-R VCD SOF Lock-sector Password EOF request <-t1-> SOF Lock-sector Password response EOF Lock sequence when error M24LR64-R M24LR64-R <---------------- Wt ------------> SOF Lock-sector Password EOF response 100/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.16 Present-sector Password On receiving the Present-sector Password command, the M24LR64-R compares the requested password with the data contained in the request and reports whether the operation has been successful in the response. The Option_flag is supported. During the comparison cycle equal to Wt, there should be no modulation (neither 100% nor 10%) otherwise, the M24LR64-R the Password value may not be correctly compared. The Wt time is equal to t1nom + 18 x 302 s. After a successful command, the access to all the memory blocks linked to the password is changed as described in Section 4.1: M24LR64-R RF block security. Table 80. Present-sector Password request format PresentIC sector Mfg Password code B3h 02h UID(1) 64 bits Password number 8 bits Data 32 bits CRC16 16 bits Request EOF Request Request SOF _flags 8 bits 1. Gray means that the field is optional. Request parameter: UID (optional) Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error) Data Present-sector Password response format when Error_flag is NOT set Response_flags 8 bits CRC16 16 bits Response EOF Table 81. Response SOF Response parameter: No parameter. The response is send back after the write cycle. Present-sector Password response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Table 82. Response SOF Response parameter: Error code as Error_flag is set: - - - - 02h: the command is not recognized, for example: a format error occurred 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available Doc ID 15170 Rev 10 101/128 Commands codes M24LR64-R Figure 66. Present-sector Password frame exchange between VCD and M24LR64-R VCD SOF Presentsector Password request EOF M24LR64-R <-t1-> SOF Presentsector Password response EOF sequence when error M24LR64-R <---------------- Wt ------------> SOF Presentsector Password response EOF 102/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.17 Fast Read Single Block On receiving the Fast Read Single Block command, the M24LR64-R reads the requested block and sends back its 32-bit value in the response. The Option_flag is supported. The data rate of the response is multiplied by 2. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. Table 83. Fast Read Single Block request format Fast Read IC Mfg Single code Block C0h 02h UID(1) 64 bits Block number 16 bits CRC16 16 bits Request EOF Request Request_ SOF flags 8 bits 1. Gray means that the field is optional. Request parameters: Option_flag UID (optional) Block number Fast Read Single Block response format when Error_flag is NOT set Sector security status(1) 8 bits Data 32 bits CRC16 16 bits Response EOF Table 84. Response Response SOF _flags 8 bits 1. Gray means that the field is optional. Response parameters: Sector security status if Option_flag is set (see Table 85) 4 bytes of block data Sector security status b6 b5 b4 b3 b2 b1 b0 0: Current sector not locked 1: Current sector locked password control bits Read / Write protection bits Table 85. b7 Reserved for future used. All at 0 Table 86. Response SOF Fast Read Single Block response format when Error_flag is set Response_ flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Doc ID 15170 Rev 10 103/128 Commands codes Response parameter: M24LR64-R Error code as Error_flag is set: - - - - - 02h: the command is not recognized, for example: a format error occurred 03h: the option is not supported 0Fh: error with no information given 10h: the specified block is not available 15h: the specified block is read protected Figure 67. Fast Read Single Block frame exchange between VCD and M24LR64-R Fast Read Single Block EOF request <-t1-> SOF Fast Read Single Block response EOF VCD M24LR64 -R SOF 104/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.18 Fast Inventory Initiated Before receiving the Fast Inventory Initiated command, the M24LR64-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64-R does not answer to the Fast Inventory Initiated command. On receiving the Fast Inventory Initiated request, the M24LR64-R runs the anticollision sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is shown in Table 26: Request flags 5 to 8 when Bit 3 = 1. The data rate of the response is multiplied by 2. The request contains: the flags, the Inventory command code the AFI if the AFI flag is set the mask length the mask value the CRC The M24LR64-R does not generate any answer in case of error. Table 87. Fast Inventory Initiated request format Mask value 0 - 64 bits CRC16 16 bits Request EOF Fast Request Request IC Mfg Optional Mask Inventory SOF _flags code AFI length Initiated 8 bits C1h 02h 8 bits 8 bits The Response contains: the flags the Unique ID Fast Inventory Initiated response format UID 64 bits CRC16 16 bits Response EOF Table 88. Response Response DSFID SOF _flags 8 bits 8 bits During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value of t3 is: t3min = 4384/fC (323.3s) + tSOF If the VCD sends a 10% modulated EOF, the minimum value of t3 is: t3min = 4384/fC (323.3s) + tNRT tSOF is the time required by the M24LR64-R to transmit an SOF to the VCD tNRT is the nominal response time of the M24LR64-R where: Doc ID 15170 Rev 10 105/128 Commands codes M24LR64-R tNRT and tSOF are dependent on the M24LR64-R-to-VCD data rate and subcarrier modulation mode. 26.19 Fast Initiate On receiving the Fast Initiate command, the M24LR64-R will set the internal Initiate_flag and send back a response only if it is in the Ready state. The command has to be issued in the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an error occurs, the M24LR64-R does not generate any answer. The Initiate_flag is reset after a power off of the M24LR64-R. The data rate of the response is multiplied by 2. The request contains: No data Fast Initiate request format Request_flags 8 bits Fast Initiate C2h IC Mfg Code 02h CRC16 16 bits Request EOF Table 89. Request SOF The response contains: the flags the Unique ID Fast Initiate response format UID 64 bits CRC16 16 bits Response EOF Table 90. Response Response DSFID SOF _flags 8 bits 8 bits Figure 68. Fast Initiate frame exchange between VCD and M24LR64-R VCD M24LR64R SOF Fast Initiate request EOF <-t1-> SOF Fast Initiate response EOF 106/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.20 Fast Read Multiple Block On receiving the Fast Read Multiple Block command, the M24LR64-R reads the selected blocks and sends back their value in multiples of 32 bits in the response. The blocks are numbered from '00h to '7FFh' in the request and the value is minus one (-1) in the field. For example, if the "number of blocks" field contains the value 06h, 7 blocks are read. The maximum number of blocks is fixed to 32 assuming that they are all located in the same sector. If the number of blocks overlaps sectors, the M24LR64-R returns an error code. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code. The Option_flag is supported. The data rate of the response is multiplied by 2. Table 91. Fast Read Multiple Block request format Fast Read Multiple Block C3h IC Mfg code 02h UID(1) First Number Request block of CRC16 EOF number blocks 16 bits 8 bits 16 bits Request Request_ SOF flags 8 bits 64 bits 1. Gray means that the field is optional. Request parameters: Option_flag UID (Optional) First block number Number of blocks Fast Read Multiple Block response format when Error_flag is NOT set Sector security status(1) 8 bits(2) Data 32 bits(2) CRC16 16 bits Response EOF Table 92. Response Response_ SOF flags 8 bits 1. Gray means that the field is optional. 2. Repeated as needed. Response parameters: Sector security status if Option_flag is set (see Table 93: Sector security status if Option_flag is set) N block of data Sector security status if Option_flag is set b6 b5 b4 b3 b2 b1 b0 0: Current sector not locked 1: Current sector locked password control bits Read / Write protection bits Table 93. b7 Reserved for future use. All at 0 Doc ID 15170 Rev 10 107/128 Commands codes Table 94. M24LR64-R Fast Read Multiple Block response format when Error_flag is set Response_flags 8 bits Error code 8 bits CRC16 16 bits Response EOF Response SOF Response parameter: Error code as Error_flag is set: - - 0Fh: other error 10h: block address not available Figure 69. Fast Read Multiple Block frame exchange between VCD and M24LR64-R Fast Read Multiple Block request VCD SOF EOF Fast Read Multiple Block response M24LR64-R <-t1-> SOF EOF 108/128 Doc ID 15170 Rev 10 M24LR64-R Commands codes 26.21 Inventory Initiated Before receiving the Inventory Initiated command, the M24LR64-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64-R does not answer to the Inventory Initiated command. On receiving the Inventory Initiated request, the M24LR64-R runs the anticollision sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is given in Table 26: Request flags 5 to 8 when Bit 3 = 1. The request contains: the flags, the Inventory Command code the AFI if the AFI flag is set the mask length the mask value the CRC The M24LR64-R does not generate any answer in case of error. Table 95. Inventory Initiated request format IC Optional Mask Mfg AFI length code 02h 8 bits 8 bits Mask value 0 - 64 bits CRC16 16 bits Request EOF Request Request Inventory SOF _flags Initiated 8 bits D1h The response contains: the flags the Unique ID Inventory Initiated response format DSFID 8 bits UID 64 bits CRC16 16 bits Response EOF Table 96. Response Response SOF _flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t3 before sending an EOF to switch to the next slot. t3 starts from the rising edge of the request EOF sent by the VCD. If the VCD sends a 100% modulated EOF, the minimum value of t3 is: t3min = 4384/fC (323.3s) + tSOF If the VCD sends a 10% modulated EOF, the minimum value of t3 is: t3min = 4384/fC (323.3s) + tNRT tSOF is the time required by the M24LR64-R to transmit an SOF to the VCD tNRT is the nominal response time of the M24LR64-R where: tNRT and tSOF are dependent on the M24LR64-R-to-VCD data rate and subcarrier modulation mode. Doc ID 15170 Rev 10 109/128 Commands codes M24LR64-R 26.22 Initiate On receiving the Initiate command, the M24LR64-R will set the internal Initiate_flag and send back a response only if it is in the ready state. The command has to be issued in the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an error occurs, the M24LR64-R does not generate any answer. The Initiate_flag is reset after a power off of the M24LR64-R. The request contains: No data Initiate request format Initiate D2h IC Mfg code 02h CRC16 16 bits Request EOF Table 97. Request Request_flags SOF 8 bits The response contains: the flags the Unique ID Initiate Initiated response format DSFID 8 bits UID 64 bits CRC16 16 bits Response EOF Table 98. Response Response SOF _flags 8 bits Figure 70. Initiate frame exchange between VCD and M24LR64-R VCD M24LR64 -R SOF Initiate request EOF <-t1-> SOF Initiate response EOF 110/128 Doc ID 15170 Rev 10 M24LR64-R Maximum rating 27 Maximum rating Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 99. Symbol TA Absolute maximum ratings Parameter Ambient operating temperature Min. -40 15 Max. 85 25 6(1) Unit C C months TSTG, Storage conditions hSTG, tSTG Sawn wafer on UV tape kept in its original packing form -65 150 C C V V mA V TSTG TLEAD VIO VCC ICC VMAX Storage temperature Lead temperature during soldering I2C input or output range I2C supply voltage RF supply current on AC0 / AC1 RF input voltage on AC0 / AC1 Electrostatic discharge voltage (human body model)(3) UFDFPN8 (MLP8), SO8, TSSOP8 UFDFPN8 (MLP8), SO8, TSSOP8 see note (2) -0.50 -0.50 -20 -7 6.0 6.0 20 7 800 3000 100 AC0, AC1 Other pads -800 -3000 -100 VESD V Electrostatic discharge voltage (Machine model) 1. Counted from ST shipment date. 2. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1 = 100 pF, R1 = 1500 , R2 = 500 ) Doc ID 15170 Rev 10 111/128 I2C DC and AC parameters M24LR64-R 28 I2C DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device in I2C mode. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 100. I2C operating conditions Symbol VCC TA Supply voltage Ambient operating temperature Parameter Min. 1.8 -40 Max. 5.5 85 Unit V C Table 101. AC test measurement conditions Symbol CL Load capacitance Input rise and fall times Input levels Input and output timing reference levels Parameter Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V Figure 71. AC test measurement I/O waveform Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC AI00825B 0.2VCC Table 102. Input parameters Symbol CIN CIN tNS(1) Parameter Input capacitance (SDA) Input capacitance (other pins) Pulse width ignored (Input filter on SCL and SDA) Min. Max. 8 6 80 Unit pF pF ns 1. Characterized only. 112/128 Doc ID 15170 Rev 10 M24LR64-R Table 103. I2C DC characteristics Symbol ILI ILO Parameter Input leakage current (SCL, SDA, E1, E0) Output leakage current Test condition VIN = VSS or VCC device in Standby mode I2C DC and AC parameters Min. Max. 2 2 100 200 500 300(2) 400(2) 700(2) 30 30 40 Unit A A SDA in Hi-Z, external voltage applied on SDA: VSS or VCC VCC = 1.8 V, fc = 400 kHz (rise/fall time < 50 ns) ICC Supply current (Read)(1) VCC = 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) VCC = 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) During tW, VCC = 1.8 V A ICC0 Supply current (Write)(1) During tW, VCC = 2.5 V During tW, VCC = 5.5 V VIN = VSS or VCC VCC = 1.8 V A ICC1 Standby supply current VIN = VSS or VCC VCC = 2.5 V VIN = VSS or VCC VCC = 5.5 V VCC = 1.8 V -0.45 -0.45 -0.45 0.75VCC 0.75VCC 0.7VCC A 0.25VCC 0.25VCC 0.3VCC VCC+1 VCC+1 VCC+1 0.4 V V V VIL Input low voltage (SDA, SCL) VCC = 2.5 V VCC = 5.5 V VCC = 1.8 V VIH Input high voltage (SDA, SCL) VCC = 2.5 V VCC = 5.5 V VOL Output low voltage IOL = 2.1 mA, VCC = 1.8 V or IOL = 3 mA, VCC = 5.5 V 1. SCL, SDA according to AC input waveform Figure 71. E0, E1 connected to Ground or VCC 2. Characterized value, not tested in production. Doc ID 15170 Rev 10 113/128 I2C DC and AC parameters Table 104. I2C AC characteristics Test conditions specified in Table 100 Symbol fC tCHCL tCLCH tXH1XH2(1) tXL1XL2(1) tDL1DL2 tDXCX tCLDX tCLQX tCLQV(2)(3) tCHDX(4) tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tR tF tF Clock frequency Clock pulse width high Clock pulse width low Input signal rise time Input signal fall time SDA (out) fall time 600 1300 20 20 20 100 0 100 100 600 600 600 1300 Parameter Min. M24LR64-R Max. 400 Unit kHz ns ns 300 300 100 ns ns ns ns ns ns tSU:DAT Data in set up time tHD:DAT Data in hold time tDH tAA Data out hold time Clock low to next data valid (access time) 900 ns ns ns ns ns tSU:STA Start condition set up time tHD:STA Start condition hold time tSU:STO Stop condition set up time tBUF Time between Stop condition and next Start condition IC write time 5 ms 1. Values recommended by the IC-bus Fast-Mode specification. 2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus x Cbus time constant is less than 500 ns (as specified in Figure 4). 4. For a reStart condition, or following a write cycle. 114/128 Doc ID 15170 Rev 10 M24LR64-R Figure 72. I2C AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDL Start condition tXH1XH2 SDA Input tCLDX SDA tDXCH Change tXL1XL2 tCHCL tCLCH I2C DC and AC parameters tCHDH tDHDL Start Stop condition condition SCL SDA In tW tCHDH Stop condition Write cycle tCHDL Start condition tCHCL SCL tCLQV SDA Out Data valid tCLQX Data valid AI00795e tQL1QL2 Doc ID 15170 Rev 10 115/128 RF DC and AC parameters M24LR64-R 29 RF DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device in RF mode. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 105. RF AC characteristics(1) (2) Symbol fCC H_ISO H_Extended Parameter External RF signal frequency Operating field according to ISO Operating field in extended temperature range 10% carrier modulation index(3) (4) MI=(A-B)/(A+B) 10% rise and fall time 10% minimum pulse width for bit 100% carrier modulation index 100% rise and fall time 100% minimum pulse width for bit Bit pulse jitter Minimum time from carrier generation to first data Subcarrier frequency high Subcarrier frequency low Time for M24LR64-R response Time between commands RF write time (including internal Verify) From H-field min FCC/32 FCC/28 4224/FS 4224/FS 318.6 309 MI=(A-B)/(A+B) TA = 0 C to 50 C TA = -40 C to 85 C 150 mA/m > H_ISO > 1000 mA/m H_ISO > 1000 mA/m Condition Min Typ Max Unit 13.553 13.56 13.567 MHz 150 150 15 10 0.5 7.1 95 0.5 7.1 -2 0.1 423.75 484.28 320.9 311.5 5.75 323.3 314 5000 3500 30 % 30 3.0 9.44 100 3.5 9.44 +2 1 s s % s s s ms kHz kHz s s ms mA/ m mA/ m MICARRIER tRFR, tRFF tRFSBL MICARRIER tRFR, tRFF tRFSBL tJIT tMIN CD fSH fSL t1 t2 Wt 1. TA = -40 to 85 C. 2. All timing measurements were performed between 0 C and 50 C on a reference antenna with the following characteristics: External size: 75 mm x 48 mm Number of turns: 5 Width of conductor: 5 mm Space between 2 conductors: 0.3 mm Value of the tuning capacitor in SO8: 27.5 pF (M24LR64-R) Value of the coil: 5 H Tuning frequency: 13.56 MHz. 3. Characterized only, not 100% tested 4. 15% (or more) carrier modulation index offers a better signal/noise ratio and therefore a wider operating range with a better noise immunity 116/128 Doc ID 15170 Rev 10 M24LR64-R Table 106. RF DC characteristics(1) Symbol VCC VBACK ICC CTUN Parameter Limited voltage Backscattered level as defined by ISO test Read Supply current Write Internal tuning capacitor in SO8(2) ISO10373-7 VCC = 2.0 V VCC = 2.0 V f = 13.56 MHz Test conditions RF DC and AC parameters Min. Typ. Max. 2.0 Unit V mV 10 50 150 24.8 27.5 30.2 A A pF 1. TA = -40 to 85 C. 2. Characterised only, at room temperature only, measured at VAC0-AC1 = 0.5 V peak. Table 107. Operating conditions Symbol TA Parameter Ambient operating temperature Min. -40 Max. 85 Unit C Figure 73 shows an ASK modulated signal, from the VCD to the M24LR64-R. The test condition for the AC/DC parameters are: Close coupling condition with tester antenna (1 mm) M24LR64-R performance measured at the tag antenna Figure 73. M24LR64-R synchronous timing, transmit and receive A B tRFF tRFR fCC tRFSBL tMAX tMIN CD AI06680 Doc ID 15170 Rev 10 117/128 Package mechanical data M24LR64-R 30 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 74. SO8N - 8-lead plastic small outline, 150 mils body width, package outline h x 45 A2 b e 0.25 mm GAUGE PLANE k 8 A ccc c D E1 1 E A1 L L1 SO-A 1. Drawing is not to scale. Table 108. SO8N - 8-lead plastic small outline, 150 mils body width, package data millimeters Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 1.04 4.90 6.00 3.90 1.27 4.80 5.80 3.80 - 0.25 0 0.40 0.10 1.25 0.28 0.17 0.48 0.23 0.10 5.00 6.20 4.00 - 0.50 8 1.27 0.0410 0 0.0157 8 0.0500 0.1929 0.2362 0.1535 0.0500 0.1890 0.2283 0.1496 - Min Max 1.75 0.25 0.0039 0.0492 0.0110 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 - Typ Min Max 0.0689 0.0098 inches(1) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 118/128 Doc ID 15170 Rev 10 M24LR64-R Package mechanical data Figure 75. UFDFPN8 (MLP8) - Ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline D L3 e b L1 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. Table 109. UFDFPN8 (MLP8) - Ultra thin fine pitch dual flat package no lead 2 x 3 mm, package mechanical data millimeters Symbol Typ A A1 b D D2 E E2 e L L1 L3 ddd(2) 0.3 0.08 0.55 0.02 0.25 2 1.6 3 0.2 0.5 0.45 Min 0.45 0 0.2 1.9 1.5 2.9 0.1 0.4 Max 0.6 0.05 0.3 2.1 1.7 3.1 0.3 0.5 0.15 0.0118 0.0031 Typ 0.0217 0.0008 0.0098 0.0787 0.063 0.1181 0.0079 0.0197 0.0177 Min 0.0177 0 0.0079 0.0748 0.0591 0.1142 0.0039 0.0157 Max 0.0236 0.002 0.0118 0.0827 0.0669 0.122 0.0118 0.0197 0.0059 inches(1) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Doc ID 15170 Rev 10 119/128 Package mechanical data Figure 76. TSSOP8 - 8-lead thin shrink small outline, package outline D M24LR64-R 8 5 c E1 E 1 4 A1 A CP b e A2 L L1 TSSOP8AM 1. Drawing is not to scale. Table 110. TSSOP8 - 8-lead thin shrink small outline, package mechanical data millimeters Symbol Typ A A1 A2 b c CP D e E E1 L L1 a N 8 3 0.65 6.4 4.4 0.6 1 0 8 8 2.9 6.2 4.3 0.45 1 0.05 0.8 0.19 0.09 Min Max 1.2 0.15 1.05 0.3 0.2 0.1 3.1 6.6 4.5 0.75 0.1181 0.0256 0.252 0.1732 0.0236 0.0394 0 8 0.1142 0.2441 0.1693 0.0177 0.0394 0.002 0.0315 0.0075 0.0035 Typ Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.122 0.2598 0.1772 0.0295 inches(1) 1. Values in inches are converted from mm and rounded to 4 decimal digits. 120/128 Doc ID 15170 Rev 10 M24LR64-R Part numbering 31 Part numbering Table 111. Ordering information scheme for packaged devices Example: M24LR64-R MN 6 T /2 Device type M24LR64 = Dual interface EEPROM Operating voltage R = VCC = 1.8 to 5.5 V Package MN = SO8N (150 mils width) MB = UFDFPN8 (MLP8) DW = TSSOP8 Device grade 6 = industrial: device tested with standard test flow over -40 to 85 C Option T = Tape and reel packing Capacitance /2 = 27.5 pF Doc ID 15170 Rev 10 121/128 Part numbering Table 112. Ordering information scheme for bare die devices Example: M24LR64-R S 1 8 5 M24LR64-R /2 Device type M24LR64 = Dual interface EEPROM Operating voltage R = VCC = 1.8 to 5.5 V Packing S = Sawn wafer in UV tape Wafer orientation 1 = see Note 1 Wafer size in inches 8 = 8-inch wafer (see Note 1) Wafer thickness 5 = 140 m (see Note 1) Capacitance /2 = 27.5 pF Note: 1 Refer to technical note TN0185 for details on the die delivery form. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 122/128 Doc ID 15170 Rev 10 M24LR64-R Anticollision algorithm (informative) Appendix A Anticollision algorithm (informative) The following pseudocode describes how anticollision could be implemented on the VCD, using recursivity. A.1 Algorithm for pulsed slots function function function function push (mask, address); pushes on private stack pop (mask, address); pops from private stack pulse_next_pause; generates a power pulse store(M24LR64-R_UID); stores M24LR64-R_UID function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask ; send the request mode = anticollision send_Request (Request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR64-R is inventoried then store (M24LR64-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle Doc ID 15170 Rev 10 123/128 CRC (informative) M24LR64-R Appendix B B.1 CRC (informative) CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR64-R and from M24LR64-R to VCD. Table 113. CRC definition CRC definition CRC type ISO/IEC 13239 Length 16 bits X 16 Polynomial + X12 + X5 + 1 = 8408h Direction Backward Preset FFFFh Residue F0B8h To add extra protection against shifting errors, a further transformation on the calculated CRC is made. The One's Complement of the calculated CRC is the value attached to the message for transmission. To check received messages the 2 CRC bytes are often also included in the re-calculation, for ease of use. In this case, the expected value for the generated CRC is the residue F0B8h. B.2 CRC calculation example This example in C language illustrates one method of calculating the CRC on a given set of bytes comprising a message. C-example to calculate or check the CRC16 according to ISO/IEC 13239 #define #define #define #define #define #define POLYNOMIAL0x8408// PRESET_VALUE0xFFFF CHECK_VALUE0xF0B8 x^16 + x^12 + x^5 + 1 NUMBER_OF_BYTES4// Example: 4 data bytes CALC_CRC1 CHECK_CRC0 void main() { unsigned int current_crc_value; unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3, 4, 0x91, 0x39}; int number_of_databytes = NUMBER_OF_BYTES; int calculate_or_check_crc; int i, j; calculate_or_check_crc = CALC_CRC; // calculate_or_check_crc = CHECK_CRC;// This could be an other example if (calculate_or_check_crc == CALC_CRC) { 124/128 Doc ID 15170 Rev 10 M24LR64-R number_of_databytes = NUMBER_OF_BYTES; } else // check CRC { number_of_databytes = NUMBER_OF_BYTES + 2; } current_crc_value = PRESET_VALUE; CRC (informative) for (i = 0; i < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for (j = 0; j < 8; j++) { if (current_crc_value & 0x0001) { current_crc_value = (current_crc_value >> 1) ^ POLYNOMIAL; } else { current_crc_value = (current_crc_value >> 1); } } } if (calculate_or_check_crc == CALC_CRC) { current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\n", current_crc_value); // stream // } else { if { current_crc_value is now ready to be appended to the data (first LSByte, then MSByte) // check CRC (current_crc_value == CHECK_VALUE) printf ("Checked CRC is ok (0x%04X)\n", current_crc_value); } else { printf ("Checked CRC is NOT ok (0x%04X)\n", current_crc_value); } } } Doc ID 15170 Rev 10 125/128 Application family identifier (AFI) (informative) M24LR64-R Appendix C Application family identifier (AFI) (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR64-R present only the M24LR64-R meeting the required application criteria. It is programmed by the M24LR64-R issuer (the purchaser of the M24LR64-R). Once locked, it cannot be modified. The most significant nibble of the AFI is used to code one specific or all application families, as defined in Table 114. The least significant nibble of the AFI is used to code one specific or all application subfamilies. Subfamily codes different from 0 are proprietary. Table 114. AFI coding(1) AFI Most significant nibble `0' `X' 'X `0' `1 '2 '3 '4 `5' '6 '7 8 '9 'A 'B 'C 'D 'E `F' AFI Least significant nibble `0' '0 '`Y' `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' `0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' '`0', `Y' `0', `Y' Meaning VICCs respond from All families and subfamilies 'All subfamilies of family X Only the Yth subfamily of family X Proprietary subfamily Y only Transport Financial Identification Telecommunication Medical Multimedia Gaming Data Storage Item Management Express Parcels Postal Services Airline Bags RFU RFU RFU Portable Files,... Internet services.... Mass transit, Bus, Airline,... IEP, Banking, Retail,... Access Control,... Public Telephony, GSM,... Examples / Note No applicative preselection Wide applicative preselection 1. X = '1' to 'F', Y = '1' to 'F' 126/128 Doc ID 15170 Rev 10 M24LR64-R Revision history Revision history Table 115. Document revision history Date 26-Feb-2010 06-Apr-2010 Revision 8 9 Changes Previous revisions: design and engineering phase. Initial public release. Updated Section 28 and Section 29 following product characterisation Added 8" wafer delivery form and update endurance on cover page. Updated VCC overview and replaced diode by regulator in Section 2.6: Supply voltage (VCC). Removed RF address column from Table 6: Sector Security Status Byte area and Table 14: System parameter sector. Updated hSTG in Table 99: Absolute maximum ratings. Added Table 112: Ordering information scheme for bare die devices. 24-Jun-2010 10 Doc ID 15170 Rev 10 127/128 M24LR64-R Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 128/128 Doc ID 15170 Rev 10 |
Price & Availability of M24LR64-R1006
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |